* [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 20:09 ` Conor Dooley
2025-09-02 13:19 ` Geert Uytterhoeven
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
` (9 subsequent siblings)
10 siblings, 2 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-clk, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
header file.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c8..f165df8a6f5a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
#define R9A09G047_SPI_CLK_SPI 9
#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
+#define R9A09G047_USB3_0_REF_ALT_CLK_P 12
+#define R9A09G047_USB3_0_CLKCORE 13
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
@ 2025-08-20 20:09 ` Conor Dooley
2025-09-02 13:19 ` Geert Uytterhoeven
1 sibling, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2025-08-20 20:09 UTC (permalink / raw)
To: Biju
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-clk, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 54 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
2025-08-20 20:09 ` Conor Dooley
@ 2025-09-02 13:19 ` Geert Uytterhoeven
1 sibling, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2025-09-02 13:19 UTC (permalink / raw)
To: Biju
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Biju Das, linux-clk, devicetree,
linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
On Wed, 20 Aug 2025 at 19:18, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
> header file.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
@ 2025-08-20 17:17 ` Biju
2025-09-02 13:27 ` Geert Uytterhoeven
2025-08-20 17:17 ` [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY Biju
` (8 subsequent siblings)
10 siblings, 1 reply; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Biju Das, linux-renesas-soc, linux-clk, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add USB3.0 clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a09g047-cpg.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index afd09b95fb74..e3fed4a3121a 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -16,7 +16,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
+ LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
/* External Input Clocks */
CLK_AUDIO_EXTAL,
@@ -181,6 +181,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
+ DEF_FIXED("usb30_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
+ DEF_FIXED("usb30_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -276,6 +278,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("usb30_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
+ BUS_MSTOP(7, BIT(12))),
+ DEF_MOD("usb30_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
+ BUS_MSTOP(7, BIT(14))),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -352,6 +358,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+ DEF_RST(10, 10, 4, 27), /* USB30_ARESETN */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
@ 2025-09-02 13:27 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2025-09-02 13:27 UTC (permalink / raw)
To: Biju
Cc: Michael Turquette, Stephen Boyd, Biju Das, linux-renesas-soc,
linux-clk, linux-kernel, Prabhakar Mahadev Lad
Hi Biju,
On Wed, 20 Aug 2025 at 19:18, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add USB3.0 clock and reset entries.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -16,7 +16,7 @@
>
> enum clk_ids {
> /* Core Clock Outputs exported to DT */
> - LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
> + LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
>
> /* External Input Clocks */
> CLK_AUDIO_EXTAL,
> @@ -181,6 +181,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
> CLK_PLLETH_DIV_125_FIX, 1, 1),
> DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
> CLK_PLLETH_DIV_125_FIX, 1, 1),
> + DEF_FIXED("usb30_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
> + DEF_FIXED("usb30_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
"usb3_0_..." for both, to match the public define and the clock diagram.
> };
>
> static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> @@ -276,6 +278,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> BUS_MSTOP(8, BIT(4))),
> DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
> BUS_MSTOP(8, BIT(4))),
> + DEF_MOD("usb30_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
> + BUS_MSTOP(7, BIT(12))),
> + DEF_MOD("usb30_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
> + BUS_MSTOP(7, BIT(14))),
"usb3_0_..." for both.
I cannot verify the actual clock bits, but they do lie in the empty
number space. And apparently the censor team forgot to scrub the
MSTOP bits ;-)
> DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> BUS_MSTOP(8, BIT(5)), 1),
> DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> @@ -352,6 +358,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
> DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
> DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
> DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
> + DEF_RST(10, 10, 4, 27), /* USB30_ARESETN */
I cannot verify the actual reset bits, but they do lie in the empty
number space.
USB3_0_ARESETN, for consistency with the clocks?
> DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
> DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
> DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
2025-08-20 17:17 ` [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
2025-08-20 17:17 ` [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 20:10 ` Conor Dooley
2025-08-20 17:17 ` [PATCH 04/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver Biju
` (7 subsequent siblings)
10 siblings, 1 reply; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm
Cc: Biju Das, linux-phy, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document Renesas RZ/G3E USB3.0 PHY. This IP is connected between
USB3HOST and PHY module. The main functions of the module are
as follows:
- Reset control
- Control of PHY input pins
- Monitoring of PHY output pins
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/phy/renesas,rzg3e-usb3-phy.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
new file mode 100644
index 000000000000..b86dc7a291a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.0 PHY
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ const: renesas,r9a09g047-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB bus clock
+ - description: USB 2.0 PHY reference clock
+ - description: USB 3.0 PHY reference clock
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: core
+ - const: ref_alt_clk_p
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+
+ usb-phy@15870000 {
+ compatible = "renesas,r9a09g047-usb3-phy";
+ reg = <0x15870000 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
2025-08-20 17:17 ` [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY Biju
@ 2025-08-20 20:10 ` Conor Dooley
2025-08-20 20:12 ` Conor Dooley
0 siblings, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2025-08-20 20:10 UTC (permalink / raw)
To: Biju
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 52 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
2025-08-20 20:10 ` Conor Dooley
@ 2025-08-20 20:12 ` Conor Dooley
2025-08-21 7:18 ` Biju Das
0 siblings, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2025-08-20 20:12 UTC (permalink / raw)
To: Biju
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-phy, devicetree, linux-kernel,
linux-renesas-soc, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 274 bytes --]
On Wed, Aug 20, 2025 at 09:10:07PM +0100, Conor Dooley wrote:
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
Now that I look again, same applies here with the different filename and
compatible. Copypaste mistake? Or why does the compatible not match the
filename?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
2025-08-20 20:12 ` Conor Dooley
@ 2025-08-21 7:18 ` Biju Das
2025-08-22 16:18 ` Rob Herring
0 siblings, 1 reply; 26+ messages in thread
From: Biju Das @ 2025-08-21 7:18 UTC (permalink / raw)
To: Conor Dooley, biju.das.au
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
magnus.damm, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad
Hi Conor,
Thanks for the feedback.
> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 20 August 2025 21:13
> Subject: Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
>
> On Wed, Aug 20, 2025 at 09:10:07PM +0100, Conor Dooley wrote:
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> Now that I look again, same applies here with the different filename and compatible. Copypaste mistake?
> Or why does the compatible not match the filename?
>
r9a09g047 is SoC part number which also known as RZ/G3E SoC.
I just followed the convention used in [1] and [2].
Please let me know, should I change rzg3e-usb3-phy.yaml.yaml-> r9a09g047-usb3-phy.yaml ?
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=44b91d61c505863b8ae90b7094aee5ca0dce808f
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=b2d25905366b4e6791f60e6bc76a636d1b88e6f8
Cheers,
Biju
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
2025-08-21 7:18 ` Biju Das
@ 2025-08-22 16:18 ` Rob Herring
0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2025-08-22 16:18 UTC (permalink / raw)
To: Biju Das
Cc: Conor Dooley, biju.das.au, Vinod Koul, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
magnus.damm, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad
On Thu, Aug 21, 2025 at 07:18:59AM +0000, Biju Das wrote:
> Hi Conor,
>
> Thanks for the feedback.
>
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 20 August 2025 21:13
> > Subject: Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
> >
> > On Wed, Aug 20, 2025 at 09:10:07PM +0100, Conor Dooley wrote:
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > Now that I look again, same applies here with the different filename and compatible. Copypaste mistake?
> > Or why does the compatible not match the filename?
> >
>
> r9a09g047 is SoC part number which also known as RZ/G3E SoC.
>
> I just followed the convention used in [1] and [2].
> Please let me know, should I change rzg3e-usb3-phy.yaml.yaml-> r9a09g047-usb3-phy.yaml ?
I think it is fine as-is.
Rob
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 04/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (2 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY Biju
@ 2025-08-20 17:17 ` Biju
2025-09-01 16:28 ` Vinod Koul
2025-08-20 17:17 ` [PATCH 05/11] usb: host: xhci-rcar: Move R-Car reg definitions Biju
` (6 subsequent siblings)
10 siblings, 1 reply; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel,
Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-kernel, linux-phy, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add Renesas RZ/G3E USB3.0 PHY driver. This module is connected
between USB3 Host and PHY module. The main functions of this
module are:
1) Reset control
2) Control of PHY input pins
3) Monitoring of PHY output pins
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/phy/renesas/Kconfig | 7 +
drivers/phy/renesas/Makefile | 1 +
drivers/phy/renesas/phy-rzg3e-usb3.c | 249 +++++++++++++++++++++++++++
3 files changed, 257 insertions(+)
create mode 100644 drivers/phy/renesas/phy-rzg3e-usb3.c
diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
index e342eef0640b..16211072098e 100644
--- a/drivers/phy/renesas/Kconfig
+++ b/drivers/phy/renesas/Kconfig
@@ -40,3 +40,10 @@ config PHY_RCAR_GEN3_USB3
select GENERIC_PHY
help
Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
+
+config PHY_RZ_G3E_USB3
+ tristate "Renesas RZ/G3E USB 3.0 PHY driver"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for USB 3.0 PHY found on Renesas RZ/G3E SoCs.
diff --git a/drivers/phy/renesas/Makefile b/drivers/phy/renesas/Makefile
index 8896d1919faa..0e98083f2f0c 100644
--- a/drivers/phy/renesas/Makefile
+++ b/drivers/phy/renesas/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
+obj-$(CONFIG_PHY_RZ_G3E_USB3) += phy-rzg3e-usb3.o
diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c b/drivers/phy/renesas/phy-rzg3e-usb3.c
new file mode 100644
index 000000000000..3ea521ed8f48
--- /dev/null
+++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3E USB3.0 PHY driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#define USB3_TEST_RESET 0x0000
+#define USB3_TEST_UTMICTRL2 0x0b04
+#define USB3_TEST_PRMCTRL5_R 0x0c10
+#define USB3_TEST_PRMCTRL6_R 0x0c14
+
+#define USB3_TEST_RSTCTRL 0x1000
+#define USB3_TEST_CLKCTRL 0x1004
+#define USB3_TEST_RAMCTRL 0x100c
+#define USB3_TEST_CREGCTRL 0x1010
+#define USB3_TEST_LANECONFIG0 0x1030
+
+#define USB3_TEST_RESET_PORTRESET0_CTRL BIT(9)
+#define USB3_TEST_RESET_SIDDQ BIT(3)
+#define USB3_TEST_RESET_PHY_RESET BIT(2)
+#define USB3_TEST_RESET_PORTRESET0 BIT(1)
+
+#define USB3_TEST_UTMICTRL2_CTRL_MASK GENMASK(9, 8)
+#define USB3_TEST_UTMICTRL2_MODE_MASK GENMASK(1, 0)
+
+#define USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK GENMASK(2, 1)
+
+#define USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK GENMASK(2, 0)
+
+#define USB3_TEST_RAMCTRL_SRAM_INIT_DONE BIT(2)
+
+struct rz_usb3 {
+ void __iomem *base;
+ struct reset_control *rstc;
+ bool skip_reinit;
+};
+
+static void rzg3e_phy_usb2test_phy_init(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + USB3_TEST_UTMICTRL2);
+ val |= USB3_TEST_UTMICTRL2_CTRL_MASK | USB3_TEST_UTMICTRL2_MODE_MASK;
+ writel(val, base + USB3_TEST_UTMICTRL2);
+
+ val = readl(base + USB3_TEST_PRMCTRL5_R);
+ val &= ~USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK;
+ val |= FIELD_PREP(USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK, 2);
+ writel(val, base + USB3_TEST_PRMCTRL5_R);
+
+ val = readl(base + USB3_TEST_PRMCTRL6_R);
+ val &= ~USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK;
+ val |= FIELD_PREP(USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK, 7);
+ writel(val, base + USB3_TEST_PRMCTRL6_R);
+
+ val = readl(base + USB3_TEST_RESET);
+ val &= ~USB3_TEST_RESET_SIDDQ;
+ val |= USB3_TEST_RESET_PORTRESET0_CTRL | USB3_TEST_RESET_PHY_RESET |
+ USB3_TEST_RESET_PORTRESET0;
+ writel(val, base + USB3_TEST_RESET);
+ fsleep(10);
+
+ val &= ~(USB3_TEST_RESET_PHY_RESET | USB3_TEST_RESET_PORTRESET0);
+ writel(val, base + USB3_TEST_RESET);
+ fsleep(10);
+
+ val = readl(base + USB3_TEST_UTMICTRL2);
+ val &= ~USB3_TEST_UTMICTRL2_CTRL_MASK;
+ writel(val, base + USB3_TEST_UTMICTRL2);
+
+ writel(0, base + USB3_TEST_RESET);
+}
+
+static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
+{
+ int ret;
+ u32 val;
+
+ writel(0x00000100, base + USB3_TEST_CREGCTRL);
+ writel(0x00000303, base + USB3_TEST_RSTCTRL);
+ fsleep(20);
+
+ writel(0x00000004, base + USB3_TEST_CLKCTRL);
+ writel(0x0000000d, base + USB3_TEST_LANECONFIG0);
+ writel(0x00000301, base + USB3_TEST_RSTCTRL);
+
+ ret = readl_poll_timeout_atomic(base + USB3_TEST_RAMCTRL, val,
+ val & USB3_TEST_RAMCTRL_SRAM_INIT_DONE, 1, 10000);
+ if (ret)
+ return ret;
+
+ writel(0x00000300, base + USB3_TEST_RSTCTRL);
+ writel(0x00000001, base + USB3_TEST_RAMCTRL);
+ writel(0x00000000, base + USB3_TEST_RSTCTRL);
+
+ return 0;
+}
+
+static int rzg3e_phy_usb3_init_helper(void __iomem *base)
+{
+ rzg3e_phy_usb2test_phy_init(base);
+
+ return rzg3e_phy_usb3test_phy_init(base);
+}
+
+static int rzg3e_phy_usb3_init(struct phy *p)
+{
+ struct rz_usb3 *r = phy_get_drvdata(p);
+ int ret = 0;
+
+ if (!r->skip_reinit)
+ ret = rzg3e_phy_usb3_init_helper(r->base);
+
+ return ret;
+}
+
+static const struct phy_ops rzg3e_phy_usb3_ops = {
+ .init = rzg3e_phy_usb3_init,
+ .owner = THIS_MODULE,
+};
+
+static int rzg3e_phy_usb3_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct rz_usb3 *r;
+ struct phy *phy;
+ int ret;
+
+ r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
+ if (!r)
+ return -ENOMEM;
+
+ r->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(r->base))
+ return PTR_ERR(r->base);
+
+ r->rstc = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(r->rstc))
+ return dev_err_probe(dev, PTR_ERR(r->rstc), "failed to get reset\n");
+
+ ret = reset_control_deassert(r->rstc);
+ if (ret)
+ return ret;
+
+ /*
+ * devm_phy_create() will call pm_runtime_enable(&phy->dev);
+ * And then, phy-core will manage runtime pm for this device.
+ */
+ ret = devm_pm_runtime_enable(dev);
+ if (ret < 0)
+ return ret;
+
+ phy = devm_phy_create(dev, NULL, &rzg3e_phy_usb3_ops);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy), "failed to create USB3 PHY\n");
+
+ platform_set_drvdata(pdev, r);
+ phy_set_drvdata(phy, r);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider), "failed to register PHY provider\n");
+
+ return 0;
+}
+
+static void rzg3e_phy_usb3_remove(struct platform_device *pdev)
+{
+ struct rz_usb3 *r = dev_get_drvdata(&pdev->dev);
+
+ reset_control_assert(r->rstc);
+};
+
+static int rzg3e_phy_usb3_suspend(struct device *dev)
+{
+ struct rz_usb3 *r = dev_get_drvdata(dev);
+
+ pm_runtime_put(dev);
+ reset_control_assert(r->rstc);
+ r->skip_reinit = false;
+
+ return 0;
+}
+
+static int rzg3e_phy_usb3_resume(struct device *dev)
+{
+ struct rz_usb3 *r = dev_get_drvdata(dev);
+ int ret;
+
+ ret = reset_control_deassert(r->rstc);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ goto reset_assert;
+
+ ret = rzg3e_phy_usb3_init_helper(r->base);
+ if (ret)
+ goto pm_put;
+
+ r->skip_reinit = true;
+
+ return 0;
+
+pm_put:
+ pm_runtime_put(dev);
+reset_assert:
+ reset_control_assert(r->rstc);
+ return ret;
+}
+
+static const struct dev_pm_ops rzg3e_phy_usb3_pm = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
+};
+
+static const struct of_device_id rzg3e_phy_usb3_match_table[] = {
+ { .compatible = "renesas,r9a09g047-usb3-phy" },
+ { /* Sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, rzg3e_phy_usb3_match_table);
+static struct platform_driver rzg3e_phy_usb3_driver = {
+ .driver = {
+ .name = "phy_rzg3e_usb3",
+ .of_match_table = rzg3e_phy_usb3_match_table,
+ .pm = pm_sleep_ptr(&rzg3e_phy_usb3_pm),
+ },
+ .probe = rzg3e_phy_usb3_probe,
+ .remove = rzg3e_phy_usb3_remove,
+};
+module_platform_driver(rzg3e_phy_usb3_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Renesas RZ/G3E USB3.0 PHY Driver");
+MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 04/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
2025-08-20 17:17 ` [PATCH 04/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver Biju
@ 2025-09-01 16:28 ` Vinod Koul
0 siblings, 0 replies; 26+ messages in thread
From: Vinod Koul @ 2025-09-01 16:28 UTC (permalink / raw)
To: Biju
Cc: Kishon Vijay Abraham I, Philipp Zabel, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-kernel, linux-phy, linux-renesas-soc,
Prabhakar Mahadev Lad
On 20-08-25, 18:17, Biju wrote:
> +static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
> +{
> + int ret;
> + u32 val;
> +
> + writel(0x00000100, base + USB3_TEST_CREGCTRL);
> + writel(0x00000303, base + USB3_TEST_RSTCTRL);
> + fsleep(20);
> +
> + writel(0x00000004, base + USB3_TEST_CLKCTRL);
> + writel(0x0000000d, base + USB3_TEST_LANECONFIG0);
> + writel(0x00000301, base + USB3_TEST_RSTCTRL);
Magic numbers...?
--
~Vinod
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 05/11] usb: host: xhci-rcar: Move R-Car reg definitions
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (3 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 04/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 17:17 ` [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Biju
` (5 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Mathias Nyman, Greg Kroah-Hartman, Geert Uytterhoeven,
Magnus Damm
Cc: Biju Das, linux-kernel, linux-usb, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Move xhci-rcar reg definitions to a header file for the preparation of adding
support for RZ/G3E XHCI that has different register definitions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/usb/host/xhci-rcar-regs.h | 49 +++++++++++++++++++++++++++++++
drivers/usb/host/xhci-rcar.c | 45 +---------------------------
2 files changed, 50 insertions(+), 44 deletions(-)
create mode 100644 drivers/usb/host/xhci-rcar-regs.h
diff --git a/drivers/usb/host/xhci-rcar-regs.h b/drivers/usb/host/xhci-rcar-regs.h
new file mode 100644
index 000000000000..5ecbda858be0
--- /dev/null
+++ b/drivers/usb/host/xhci-rcar-regs.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __XHCI_RCAR_H
+#define __XHCI_RCAR_H
+
+/*** Register Offset ***/
+#define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
+#define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
+#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
+#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
+
+#define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
+#define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
+#define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
+#define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
+#define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
+#define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
+
+/*** Register Settings ***/
+/* AXI Host Control Status */
+#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
+#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
+#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
+ RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
+
+/* Interrupt Enable */
+#define RCAR_USB3_INT_XHC_ENA 0x00000001
+#define RCAR_USB3_INT_PME_ENA 0x00000002
+#define RCAR_USB3_INT_HSE_ENA 0x00000004
+#define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
+ RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
+
+/* FW Download Control & Status */
+#define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
+#define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
+#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
+
+/* LCLK Select */
+#define RCAR_USB3_LCLK_ENA_VAL 0x01030001
+
+/* USB3.0 Configuration */
+#define RCAR_USB3_CONF1_VAL 0x00030204
+#define RCAR_USB3_CONF2_VAL 0x00030300
+#define RCAR_USB3_CONF3_VAL 0x13802007
+
+/* USB3.0 Polarity */
+#define RCAR_USB3_RX_POL_VAL BIT(21)
+#define RCAR_USB3_TX_POL_VAL BIT(4)
+
+#endif /* __XHCI_RCAR_H */
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index 1cc082a3b793..6d4662def87f 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -14,6 +14,7 @@
#include "xhci.h"
#include "xhci-plat.h"
+#include "xhci-rcar-regs.h"
#include "xhci-rzv2m.h"
#define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
@@ -29,50 +30,6 @@
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
-/*** Register Offset ***/
-#define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
-#define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
-#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
-#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
-
-#define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
-#define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
-#define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
-#define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
-#define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
-#define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
-
-/*** Register Settings ***/
-/* AXI Host Control Status */
-#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
-#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
-#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
- RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
-
-/* Interrupt Enable */
-#define RCAR_USB3_INT_XHC_ENA 0x00000001
-#define RCAR_USB3_INT_PME_ENA 0x00000002
-#define RCAR_USB3_INT_HSE_ENA 0x00000004
-#define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
- RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
-
-/* FW Download Control & Status */
-#define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
-#define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
-#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
-
-/* LCLK Select */
-#define RCAR_USB3_LCLK_ENA_VAL 0x01030001
-
-/* USB3.0 Configuration */
-#define RCAR_USB3_CONF1_VAL 0x00030204
-#define RCAR_USB3_CONF2_VAL 0x00030300
-#define RCAR_USB3_CONF3_VAL 0x13802007
-
-/* USB3.0 Polarity */
-#define RCAR_USB3_RX_POL_VAL BIT(21)
-#define RCAR_USB3_TX_POL_VAL BIT(4)
-
static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
{
/* LCLK Select */
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (4 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 05/11] usb: host: xhci-rcar: Move R-Car reg definitions Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 20:11 ` Conor Dooley
2025-08-22 16:20 ` Rob Herring
2025-08-20 17:17 ` [PATCH 07/11] usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv Biju
` (4 subsequent siblings)
10 siblings, 2 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-usb, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
Revision 1.0.
- Supports 1 downstream USB receptacles
- Number of SSP Gen2 or SS ports: 1
- Number of HS or FS or LS ports: 1
- Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
- Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
these split-transactions.
- Supports Power Control and Over Current Detection.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/usb/renesas,rzg3e-xhci.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
diff --git a/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
new file mode 100644
index 000000000000..2f73ea2e1e78
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.2 Gen2 Host controller
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ const: renesas,r9a09g047-xhci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Logical OR of all interrupt signals.
+ - description: System management interrupt
+ - description: Host system error interrupt
+ - description: Power management event interrupt
+ - description: xHC interrupt
+
+ interrupt-names:
+ items:
+ - const: all
+ - const: smi
+ - const: hse
+ - const: pme
+ - const: xhc
+
+ clocks:
+ maxItems: 1
+
+ phys:
+ maxItems: 2
+
+ phy-names:
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+ - phys
+ - phy-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@15850000 {
+ compatible = "renesas,r9a09g047-xhci";
+ reg = <0x15850000 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-20 17:17 ` [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Biju
@ 2025-08-20 20:11 ` Conor Dooley
2025-08-21 7:15 ` Biju Das
2025-08-22 16:20 ` Rob Herring
1 sibling, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2025-08-20 20:11 UTC (permalink / raw)
To: Biju
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-usb, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad
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On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
> Revision 1.0.
> - Supports 1 downstream USB receptacles
> - Number of SSP Gen2 or SS ports: 1
> - Number of HS or FS or LS ports: 1
> - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> these split-transactions.
> - Supports Power Control and Over Current Detection.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +---
> +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> + const: renesas,r9a09g047-xhci
How come these don't match? I don't understand your naming scheme at
all, so idk which is even correct!
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^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-20 20:11 ` Conor Dooley
@ 2025-08-21 7:15 ` Biju Das
2025-08-21 18:16 ` Conor Dooley
0 siblings, 1 reply; 26+ messages in thread
From: Biju Das @ 2025-08-21 7:15 UTC (permalink / raw)
To: Conor Dooley, biju.das.au
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, magnus.damm,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar Mahadev Lad
Hi Conor,
Thanks for the feedback.
> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 20 August 2025 21:11
> Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
>
> On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > Specification Revision 1.0.
> > - Supports 1 downstream USB receptacles
> > - Number of SSP Gen2 or SS ports: 1
> > - Number of HS or FS or LS ports: 1
> > - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > these split-transactions.
> > - Supports Power Control and Over Current Detection.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > +---
> > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
>
> > + const: renesas,r9a09g047-xhci
>
> How come these don't match? I don't understand your naming scheme at all, so idk which is even correct!
r9a09g047 is SoC part number which also known as RZ/G3E SoC.
I just followed the convention used in [1] and [2].
Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=44b91d61c505863b8ae90b7094aee5ca0dce808f
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=b2d25905366b4e6791f60e6bc76a636d1b88e6f8
Cheers,
Biju
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-21 7:15 ` Biju Das
@ 2025-08-21 18:16 ` Conor Dooley
2025-08-22 6:48 ` Biju Das
0 siblings, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2025-08-21 18:16 UTC (permalink / raw)
To: Biju Das
Cc: biju.das.au, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, magnus.damm,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar Mahadev Lad
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On Thu, Aug 21, 2025 at 07:15:59AM +0000, Biju Das wrote:
> Hi Conor,
>
> Thanks for the feedback.
>
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 20 August 2025 21:11
> > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
> >
> > On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > > Specification Revision 1.0.
> > > - Supports 1 downstream USB receptacles
> > > - Number of SSP Gen2 or SS ports: 1
> > > - Number of HS or FS or LS ports: 1
> > > - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > > High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > > - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > > these split-transactions.
> > > - Supports Power Control and Over Current Detection.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > +---
> > > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> >
> > > + const: renesas,r9a09g047-xhci
> >
> > How come these don't match? I don't understand your naming scheme at all, so idk which is even correct!
>
> r9a09g047 is SoC part number which also known as RZ/G3E SoC.
>
> I just followed the convention used in [1] and [2].
> Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?
What's the benefit of using that instead of the compatible, other than
confusing me?
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=44b91d61c505863b8ae90b7094aee5ca0dce808f
>
> [2]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=b2d25905366b4e6791f60e6bc76a636d1b88e6f8
>
> Cheers,
> Biju
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^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-21 18:16 ` Conor Dooley
@ 2025-08-22 6:48 ` Biju Das
2025-08-22 16:22 ` Conor Dooley
0 siblings, 1 reply; 26+ messages in thread
From: Biju Das @ 2025-08-22 6:48 UTC (permalink / raw)
To: Conor Dooley
Cc: biju.das.au, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, magnus.damm,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar Mahadev Lad
Hi Conor,
> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 21 August 2025 19:16
> Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
>
> On Thu, Aug 21, 2025 at 07:15:59AM +0000, Biju Das wrote:
> > Hi Conor,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor@kernel.org>
> > > Sent: 20 August 2025 21:11
> > > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E
> > > USB3HOST
> > >
> > > On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > > > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > > > Specification Revision 1.0.
> > > > - Supports 1 downstream USB receptacles
> > > > - Number of SSP Gen2 or SS ports: 1
> > > > - Number of HS or FS or LS ports: 1
> > > > - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > > > High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > > > - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > > > these split-transactions.
> > > > - Supports Power Control and Over Current Detection.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > > +---
> > > > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> > >
> > > > + const: renesas,r9a09g047-xhci
> > >
> > > How come these don't match? I don't understand your naming scheme at all, so idk which is even
> correct!
> >
> > r9a09g047 is SoC part number which also known as RZ/G3E SoC.
> >
> > I just followed the convention used in [1] and [2].
> > Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?
>
> What's the benefit of using that instead of the compatible, other than confusing me?
I guess, for an end user it will be useful to locate the document easily without any issue
Given a choice to locate a document rzg3e-xhci.yaml vs r9a09g047-xhci.yaml which one you prefer
for RZ/G3E XHCI IP?
Cheers,
Biju
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-22 6:48 ` Biju Das
@ 2025-08-22 16:22 ` Conor Dooley
0 siblings, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2025-08-22 16:22 UTC (permalink / raw)
To: Biju Das
Cc: biju.das.au, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, magnus.damm,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar Mahadev Lad
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On Fri, Aug 22, 2025 at 06:48:07AM +0000, Biju Das wrote:
> Hi Conor,
>
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 21 August 2025 19:16
> > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
> >
> > On Thu, Aug 21, 2025 at 07:15:59AM +0000, Biju Das wrote:
> > > Hi Conor,
> > >
> > > Thanks for the feedback.
> > >
> > > > -----Original Message-----
> > > > From: Conor Dooley <conor@kernel.org>
> > > > Sent: 20 August 2025 21:11
> > > > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E
> > > > USB3HOST
> > > >
> > > > On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > >
> > > > > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > > > > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > > > > Specification Revision 1.0.
> > > > > - Supports 1 downstream USB receptacles
> > > > > - Number of SSP Gen2 or SS ports: 1
> > > > > - Number of HS or FS or LS ports: 1
> > > > > - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > > > > High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > > > > - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > > > > these split-transactions.
> > > > > - Supports Power Control and Over Current Detection.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Reviewed-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> > > >
> > > > > + const: renesas,r9a09g047-xhci
> > > >
> > > > How come these don't match? I don't understand your naming scheme at all, so idk which is even
> > correct!
> > >
> > > r9a09g047 is SoC part number which also known as RZ/G3E SoC.
> > >
> > > I just followed the convention used in [1] and [2].
> > > Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?
> >
> > What's the benefit of using that instead of the compatible, other than confusing me?
>
> I guess, for an end user it will be useful to locate the document easily without any issue
If you're looking to avoid issues for end users, why are you mixing and
matching at all between the part number and the codename or w/e RZ/G3E
is?
> Given a choice to locate a document rzg3e-xhci.yaml vs r9a09g047-xhci.yaml which one you prefer
> for RZ/G3E XHCI IP?
My preference is filenames matching compatibles as the norm, but
apparently Rob doesn't give care in this case nor does Krzysztof
(seeing as they acked/applied similar stuff for the platform already) so I
won't dig my heels in.
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2025-08-20 17:17 ` [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Biju
2025-08-20 20:11 ` Conor Dooley
@ 2025-08-22 16:20 ` Rob Herring
1 sibling, 0 replies; 26+ messages in thread
From: Rob Herring @ 2025-08-22 16:20 UTC (permalink / raw)
To: Biju
Cc: Greg Kroah-Hartman, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Biju Das, linux-usb, devicetree,
linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
> Revision 1.0.
> - Supports 1 downstream USB receptacles
> - Number of SSP Gen2 or SS ports: 1
> - Number of HS or FS or LS ports: 1
> - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> these split-transactions.
> - Supports Power Control and Over Current Detection.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../bindings/usb/renesas,rzg3e-xhci.yaml | 84 +++++++++++++++++++
> 1 file changed, 84 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
> new file mode 100644
> index 000000000000..2f73ea2e1e78
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3E USB 3.2 Gen2 Host controller
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
Common USB and XHCI properties don't apply?
> +properties:
> + compatible:
> + const: renesas,r9a09g047-xhci
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: Logical OR of all interrupt signals.
> + - description: System management interrupt
> + - description: Host system error interrupt
> + - description: Power management event interrupt
> + - description: xHC interrupt
> +
> + interrupt-names:
> + items:
> + - const: all
> + - const: smi
> + - const: hse
> + - const: pme
> + - const: xhc
> +
> + clocks:
> + maxItems: 1
> +
> + phys:
> + maxItems: 2
> +
> + phy-names:
> + items:
> + - const: usb2-phy
> + - const: usb3-phy
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - power-domains
> + - resets
> + - phys
> + - phy-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + usb@15850000 {
> + compatible = "renesas,r9a09g047-xhci";
> + reg = <0x15850000 0x10000>;
> + interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "all", "smi", "hse", "pme", "xhc";
> + clocks = <&cpg CPG_MOD 0xaf>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0xaa>;
> + phys = <&usb3_phy>, <&usb3_phy>;
> + phy-names = "usb2-phy", "usb3-phy";
> + };
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 07/11] usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (5 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 17:17 ` [PATCH 08/11] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support Biju
` (3 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Mathias Nyman, Greg Kroah-Hartman
Cc: Biju Das, linux-usb, linux-kernel, Geert Uytterhoeven,
Prabhakar Mahadev Lad, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Some SoCs (eg Renesas RZ/G3E SoC) have special sequence after
xhci_resume, add .post_resume_quick for it.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/usb/host/xhci-plat.c | 14 ++++++++++++++
drivers/usb/host/xhci-plat.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 5eb51797de32..7191a63dec2a 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -74,6 +74,16 @@ static int xhci_priv_resume_quirk(struct usb_hcd *hcd)
return priv->resume_quirk(hcd);
}
+static int xhci_priv_post_resume_quirk(struct usb_hcd *hcd)
+{
+ struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
+
+ if (!priv->post_resume_quirk)
+ return 0;
+
+ return priv->post_resume_quirk(hcd);
+}
+
static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
{
struct xhci_plat_priv *priv = xhci_to_priv(xhci);
@@ -509,6 +519,10 @@ static int xhci_plat_resume_common(struct device *dev, bool power_lost)
if (ret)
goto disable_clks;
+ ret = xhci_priv_post_resume_quirk(hcd);
+ if (ret)
+ goto disable_clks;
+
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
diff --git a/drivers/usb/host/xhci-plat.h b/drivers/usb/host/xhci-plat.h
index fe4f95e690fa..4c2a89bd83a1 100644
--- a/drivers/usb/host/xhci-plat.h
+++ b/drivers/usb/host/xhci-plat.h
@@ -20,6 +20,7 @@ struct xhci_plat_priv {
int (*init_quirk)(struct usb_hcd *);
int (*suspend_quirk)(struct usb_hcd *);
int (*resume_quirk)(struct usb_hcd *);
+ int (*post_resume_quirk)(struct usb_hcd *);
};
#define hcd_to_xhci_priv(h) ((struct xhci_plat_priv *)hcd_to_xhci(h)->priv)
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 08/11] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (6 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 07/11] usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 17:17 ` [PATCH 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes Biju
` (2 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathias Nyman, Geert Uytterhoeven,
Magnus Damm, Philipp Zabel
Cc: Biju Das, Krzysztof Kozlowski, Wesley Cheng, linux-kernel,
linux-usb, linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
The USB3.2 Gen2 Host controller (a.k.a USB3HOST), IP found on the RZ/G3E
SoC is similar to R-Car XHCI, but it doesn't require any firmware.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/xhci-rcar.c | 55 ++++++++++++++++++++++++++++++
drivers/usb/host/xhci-rzg3e-regs.h | 12 +++++++
3 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/host/xhci-rzg3e-regs.h
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 109100cc77a3..c4f17ce5c77b 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -93,7 +93,7 @@ config USB_XHCI_RCAR
default ARCH_RENESAS
help
Say 'Y' to enable the support for the xHCI host controller
- found in Renesas R-Car ARM SoCs.
+ found in Renesas R-Car and RZ/G3E alike ARM SoCs.
config USB_XHCI_RZV2M
bool "xHCI support for Renesas RZ/V2M SoC"
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index 6d4662def87f..8a993ee21c87 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -11,10 +11,12 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/usb/phy.h>
+#include <linux/reset.h>
#include "xhci.h"
#include "xhci-plat.h"
#include "xhci-rcar-regs.h"
+#include "xhci-rzg3e-regs.h"
#include "xhci-rzv2m.h"
#define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
@@ -67,6 +69,48 @@ static void xhci_rcar_start(struct usb_hcd *hcd)
}
}
+static void xhci_rzg3e_start(struct usb_hcd *hcd)
+{
+ u32 int_en;
+
+ if (hcd->regs) {
+ /* Update the controller initial setting */
+ writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(0));
+ writel(0x00160200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(1));
+ writel(0x03150000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(2));
+ writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(3));
+ writel(0x00180000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(4));
+
+ /* Interrupt Enable */
+ int_en = readl(hcd->regs + RZG3E_USB3_HOST_INTEN);
+ int_en |= RZG3E_USB3_HOST_INTEN_ENA;
+ writel(int_en, hcd->regs + RZG3E_USB3_HOST_INTEN);
+ }
+}
+
+static int xhci_rzg3e_resume(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+ return reset_control_deassert(xhci->reset);
+}
+
+static int xhci_rzg3e_post_resume(struct usb_hcd *hcd)
+{
+ xhci_rzg3e_start(hcd);
+
+ return 0;
+}
+
+static int xhci_rzg3e_suspend(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+ reset_control_assert(xhci->reset);
+
+ return 0;
+}
+
static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
{
struct device *dev = hcd->self.controller;
@@ -190,6 +234,14 @@ static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
.plat_start = xhci_rzv2m_start,
};
+static const struct xhci_plat_priv xhci_plat_renesas_rzg3e = {
+ .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_RESET_ON_RESUME | XHCI_SUSPEND_RESUME_CLKS,
+ .plat_start = xhci_rzg3e_start,
+ .suspend_quirk = xhci_rzg3e_suspend,
+ .resume_quirk = xhci_rzg3e_resume,
+ .post_resume_quirk = xhci_rzg3e_post_resume,
+};
+
static const struct of_device_id usb_xhci_of_match[] = {
{
.compatible = "renesas,xhci-r8a7790",
@@ -206,6 +258,9 @@ static const struct of_device_id usb_xhci_of_match[] = {
}, {
.compatible = "renesas,xhci-r8a7796",
.data = &xhci_plat_renesas_rcar_gen3,
+ }, {
+ .compatible = "renesas,r9a09g047-xhci",
+ .data = &xhci_plat_renesas_rzg3e,
}, {
.compatible = "renesas,rcar-gen2-xhci",
.data = &xhci_plat_renesas_rcar_gen2,
diff --git a/drivers/usb/host/xhci-rzg3e-regs.h b/drivers/usb/host/xhci-rzg3e-regs.h
new file mode 100644
index 000000000000..7a244a47b882
--- /dev/null
+++ b/drivers/usb/host/xhci-rzg3e-regs.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __XHCI_RZG3E_H
+#define __XHCI_RZG3E_H
+
+#define RZG3E_USB3_HOST_INTEN 0x1044 /* Interrupt Enable */
+#define RZG3E_USB3_HOST_U3P0PIPESC(x) (0x10c0 + (x) * 4) /* PIPE Status and Control Register */
+
+#define RZG3E_USB3_HOST_INTEN_XHC BIT(0)
+#define RZG3E_USB3_HOST_INTEN_HSE BIT(2)
+#define RZG3E_USB3_HOST_INTEN_ENA (RZG3E_USB3_HOST_INTEN_XHC | RZG3E_USB3_HOST_INTEN_HSE)
+
+#endif /* __XHCI_RZG3E_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (7 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 08/11] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 17:17 ` [PATCH 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST Biju
2025-08-20 17:17 ` [PATCH 11/11] arm64: defconfig: Enable RZ/G3E USB3 PHY driver Biju
10 siblings, 0 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add USB3 PHY/Host nodes to RZ/G3E ("R9A09G047") SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e5b24e46d645..b3ef0c15e62d 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -836,6 +836,36 @@ gic: interrupt-controller@14900000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ xhci: usb@15850000 {
+ compatible = "renesas,r9a09g047-xhci";
+ reg = <0 0x15850000 0 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3_phy: usb-phy@15870000 {
+ compatible = "renesas,r9a09g047-usb3-phy";
+ reg = <0 0x15870000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>,
+ <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>,
+ <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (8 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes Biju
@ 2025-08-20 17:17 ` Biju
2025-08-20 17:17 ` [PATCH 11/11] arm64: defconfig: Enable RZ/G3E USB3 PHY driver Biju
10 siblings, 0 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Enable USB3.2 Gen2 Host controller(a.k.a USB3HOST) on the RZ/G3E SMARC EVK
platform.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 10 ++++++++++
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..0fd90d79b020 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -164,6 +164,11 @@ sd1-data {
<RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
};
};
+
+ usb3_pins: usb3 {
+ pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */
+ <RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */
+ };
};
&scif0 {
@@ -179,3 +184,8 @@ &sdhi1 {
vmmc-supply = <®_3p3v>;
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};
+
+&xhci {
+ pinctrl-0 = <&usb3_pins>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 58561da3007a..8b3765b8267d 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -106,3 +106,11 @@ &sdhi1 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 11/11] arm64: defconfig: Enable RZ/G3E USB3 PHY driver
2025-08-20 17:17 [PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (9 preceding siblings ...)
2025-08-20 17:17 ` [PATCH 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST Biju
@ 2025-08-20 17:17 ` Biju
10 siblings, 0 replies; 26+ messages in thread
From: Biju @ 2025-08-20 17:17 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Biju Das, Krzysztof Kozlowski, Geert Uytterhoeven,
Bjorn Andersson, Arnd Bergmann, Nishanth Menon, Eric Biggers,
Nícolas F. R. A. Prado, Taniya Das, Lad Prabhakar,
Kuninori Morimoto, linux-arm-kernel, linux-kernel, Biju Das,
linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Enable the RZ/G3E USB3 PHY driver on the Renesas RZ/G3E SMARC EVK board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7cf21ca6a860..110142ab2f82 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1643,6 +1643,7 @@ CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
+CONFIG_PHY_RZ_G3E_USB3=m
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
--
2.43.0
^ permalink raw reply related [flat|nested] 26+ messages in thread