From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: linux-renesas-soc@vger.kernel.org
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>
Subject: [PATCH] soc: renesas: rcar-rst: keep RESBAR2S in default state
Date: Fri, 17 Oct 2025 13:42:34 +0200 [thread overview]
Message-ID: <20251017114234.2968-2-wsa+renesas@sang-engineering.com> (raw)
Unlike Gen2, Gen4 has bit 15 of WDTRSTCR register also used. Keep it in
the default state for the V3U firmware workaround.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/soc/renesas/rcar-rst.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 7ba02f3a4a4f..0541990901fc 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -12,6 +12,7 @@
#define WDTRSTCR_RESET 0xA55A0002
#define WDTRSTCR 0x0054
+#define GEN4_WDTRSTCR_RESET 0xA55A8002
#define GEN4_WDTRSTCR 0x0010
#define CR7BAR 0x0070
@@ -30,7 +31,7 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base)
static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base)
{
- iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
+ iowrite32(GEN4_WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
return 0;
}
--
2.47.2
next reply other threads:[~2025-10-17 11:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 11:42 Wolfram Sang [this message]
2025-10-20 13:15 ` [PATCH] soc: renesas: rcar-rst: keep RESBAR2S in default state Geert Uytterhoeven
2025-10-20 19:46 ` Wolfram Sang
2025-10-21 7:41 ` Geert Uytterhoeven
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