[RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: use interrupt for Micrel PHYs

[RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: use interrupt for Micrel PHYs

[Wolfram Sang]

Make use of the interrupts wired to the Micrel PHYs via the GPIO IRQ
mux.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Works nicely and kinda out-of-the-box for the Micrel PHYs, couldn't get
it to work (reliably?) with the Marvell PHYs on the EB. Leaving this for
later (if ever), no more bandwidth currently. But at least we have an
upstream user for the gpioirqmux now.

RFC because Hervé's patches are still in-flight.

 .../dts/renesas/r9a06g032-rzn1d400-db.dts     | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
index c3786d54992a..d81e92f787a6 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
@@ -186,6 +186,12 @@ fixed-link {
 	};
 };
 
+&gpioirqmux {
+	interrupt-map = <89 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* pin 147: phy@4 */
+			<91 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* pin 149: phy@5 */
+	status = "okay";
+};
+
 #if DB_SW2_2 == SW_OFF
 &gpio1 {
 	pinctrl-0 = <&pins_gpio1>;
@@ -194,6 +200,12 @@ &gpio1 {
 };
 #endif
 
+&gpio2 {
+	pinctrl-0 = <&pins_gpio2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &i2c2 {
 	pinctrl-0 = <&pins_i2c2>;
 	pinctrl-names = "default";
@@ -286,6 +298,13 @@ pins_gpio1: pins-gpio1 {
 	};
 #endif
 
+	pins_gpio2: pins-gpio2 {
+		pinmux = <RZN1_PINMUX(147, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(149, RZN1_FUNC_GPIO)>;
+		drive-strength = <6>;
+		bias-disable;
+	};
+
 	pins_eth3: pins_eth3 {
 		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
 			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
@@ -355,11 +374,13 @@ mdio {
 		switch0phy4: ethernet-phy@4 {
 			reg = <4>;
 			micrel,led-mode = <1>;
+			interrupts-extended = <&gpio2a 25 IRQ_TYPE_LEVEL_LOW>;
 		};
 
 		switch0phy5: ethernet-phy@5 {
 			reg = <5>;
 			micrel,led-mode = <1>;
+			interrupts-extended = <&gpio2a 27 IRQ_TYPE_LEVEL_LOW>;
 		};
 	};
 };
-- 
2.47.2

Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: use interrupt for Micrel PHYs

[Herve Codina]

Hi Wolfram,

On Wed,  1 Oct 2025 12:38:06 +0200
Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:

> Make use of the interrupts wired to the Micrel PHYs via the GPIO IRQ
> mux.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> 
> Works nicely and kinda out-of-the-box for the Micrel PHYs, couldn't get
> it to work (reliably?) with the Marvell PHYs on the EB. Leaving this for
> later (if ever), no more bandwidth currently. But at least we have an
> upstream user for the gpioirqmux now.
> 
> RFC because Hervé's patches are still in-flight.

Yes and v5 has been sent:
  https://lore.kernel.org/lkml/20251020080648.13452-1-herve.codina@bootlin.com/

This v5 iteration should impact modification done in this RFC.

> 
>  .../dts/renesas/r9a06g032-rzn1d400-db.dts     | 21 +++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 

Reviewed-by: Herve Codina <herve.codina@bootlin.com>

Best regards,
Hervé

Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: use interrupt for Micrel PHYs

[Wolfram Sang]

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Hi Herve,

> This v5 iteration should impact modification done in this RFC.

What do you mean with "impact"? The patch works fine with your v6
series.

Happy hacking,

   Wolfram


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Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: use interrupt for Micrel PHYs

[Herve Codina]

On Tue, 28 Oct 2025 10:08:54 +0100
Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:

> Hi Herve,
> 
> > This v5 iteration should impact modification done in this RFC.  
> 
> What do you mean with "impact"? The patch works fine with your v6
> series.

Oups,

s/should/should not/

Sorry for the noise.

Best regards,
Hervé


-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [RFC PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-db: use interrupt for Micrel PHYs

[Wolfram Sang]

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> > > This v5 iteration should impact modification done in this RFC.  
> > 
> > What do you mean with "impact"? The patch works fine with your v6
> > series.
> 
> Oups,
> 
> s/should/should not/

:) Thanks for confirming.


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