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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:50 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 5/6] arm: dts: renesas: r8a7740: Add clocks for FSI Date: Mon, 13 Apr 2026 17:06:59 +0700 Message-ID: <20260413100700.30995-6-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc Add the SPU clock to the FSI node to ensure it is enabled before register access, preventing potential system hangs. Also complete the FSI clock tree by adding: - CPG DIV6 clocks (icka/b) as functional parents - External clocks (xcka/b) from the board Define fsib nodes to support the clock hierarchy. Signed-off-by: bui duc phuc --- Changes in v2: - Rename "fsi" clock to "own" to match driver implementation. - Add missing clock names: "icka", "ickb", "xcka", "xckb". arch/arm/boot/dts/renesas/r8a7740.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index d13ab86c3ab4..b8d903b711be 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -393,7 +393,11 @@ sh_fsi2: sound@fe1f0000 { compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsiack_clk>, + <&fsibck_clk>; + clock-names = "own", "spu", "icka", "ickb", "xcka", + "xckb"; power-domains = <&pd_a4mp>; status = "disabled"; }; @@ -614,6 +618,12 @@ vou_clk: vou@e6150088 { <0>; #clock-cells = <0>; }; + fsib_clk: fsib@e6150090 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150090 4>; + clocks = <&pllc1_div2_clk>, <&fsibck_clk>, <0>, <0>; + #clock-cells = <0>; + }; stpro_clk: stpro@e615009c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; -- 2.43.0