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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:29 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 10/10] ASoC: renesas: fsi: Add SPU clock control in hw_startup/shutdown Date: Sun, 10 May 2026 15:43:03 +0700 Message-ID: <20260510084303.122426-11-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc Enable and disable the SPU clock in fsi_hw_startup() and fsi_hw_shutdown() to ensure the clock is active while the driver accesses hardware registers. Previously, the SPU clock was enabled by the bootloader and remained active during operation. However, after adding the SPU clock to the device tree, it is disabled automatically once the system initialization completes. As a result, register accesses may occur while the clock is disabled, which can lead to system hangs. Manage the SPU clock explicitly in the driver to ensure correct behavior. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index c3ac8b30f342..5307085c0615 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -1579,6 +1579,19 @@ static int fsi_hw_startup(struct fsi_priv *fsi, struct device *dev) { u32 data = 0; + int ret; + + /* enable spu clock */ + if (fsi->master->clk_spu) { + scoped_guard(spinlock_irqsave, &fsi->master->lock) { + if (fsi->master->spu_count == 0) { + ret = clk_enable(fsi->master->clk_spu); + if (ret < 0) + return ret; + } + fsi->master->spu_count++; + } + } /* clock setting */ if (fsi_is_clk_master(fsi)) @@ -1636,6 +1649,12 @@ static int fsi_hw_shutdown(struct fsi_priv *fsi, /* stop master clock */ if (fsi_is_clk_master(fsi)) return fsi_clk_disable(dev, fsi); + if (fsi->master->clk_spu) { + scoped_guard(spinlock_irqsave, &fsi->master->lock) { + if (--fsi->master->spu_count == 0) + clk_disable(fsi->master->clk_spu); + } + } return 0; } -- 2.43.0