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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:43:46 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc , Geert Uytterhoeven Subject: [PATCH v3 01/10] ASoC: dt-bindings: renesas,fsi: add support multiple clocks Date: Sun, 10 May 2026 15:42:54 +0700 Message-ID: <20260510084303.122426-2-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before accessing its registers. Without this clock, any register access leads to a system hang as the FSI block sits behind the SPU bus. Update the binding to support multiple clocks to properly describe the hardware clock tree, including: - SPU bus/bridge clock (spu) for register access. - CPG DIV6 clocks (icka/b) as functional clock parents. - FSI internal dividers (diva/b) for audio clock generation. - External clock inputs (xcka/b) provided by the board. Suggested-by: Geert Uytterhoeven Signed-off-by: bui duc phuc --- .../bindings/sound/renesas,fsi.yaml | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml index df91991699a7..c50e7115b21a 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -38,7 +38,32 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Main FSI module clock + - description: | + SPU bus/bridge clock. On R8A7740, this clock must be enabled to allow + register access as the FSI block is connected behind the SPU bus. + - description: CPG DIV6 functional clocks for FSI port A + - description: CPG DIV6 functional clocks for FSI port B + - description: Internal FSI dividers for port A used for audio clock generation + - description: Internal FSI dividers for port B used for audio clock generation + - description: External clock inputs for FSI port A provided by the board + - description: External clock inputs for FSI port B provided by the board + + clock-names: + minItems: 1 + maxItems: 8 + items: + enum: + - fck # Main FSI module clock + - spu # optional SPU bus/bridge clock + - icka # optional CPG DIV6 functional clocks for FSI port A + - ickb # optional CPG DIV6 functional clocks for FSI port B + - diva # optional Internal FSI dividers for port A used for audio clock generation + - divb # optional Internal FSI dividers for port B used for audio clock generation + - xcka # optional External clock inputs for FSI port A provided by the board + - xckb # optional External clock inputs for FSI port B provided by the board power-domains: maxItems: 1 -- 2.43.0