From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:59714 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728459AbeIQRuU (ORCPT ); Mon, 17 Sep 2018 13:50:20 -0400 From: Laurent Pinchart To: Ulrich Hecht Cc: Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Kieran Bingham Subject: Re: [PATCH v2 04/16] drm: bridge: thc63: Restrict modes based on hardware operating frequency Date: Mon, 17 Sep 2018 15:23:28 +0300 Message-ID: <3450184.KxzLXOijW3@avalon> In-Reply-To: <891115091.239809.1537181623129@webmail.strato.com> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <20180914091046.483-5-laurent.pinchart+renesas@ideasonboard.com> <891115091.239809.1537181623129@webmail.strato.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Ulrich, On Monday, 17 September 2018 13:53:43 EEST Ulrich Hecht wrote: > > On September 14, 2018 at 11:10 AM Laurent Pinchart wrote: > > > > The THC63LVD1024 is restricted to a pixel clock frequency in the range > > of 8 to 135 MHz. Implement the bridge .mode_valid() operation > > accordingly. > > > > Signed-off-by: Laurent Pinchart > > > > Reviewed-by: Andrzej Hajda > > Tested-by: Jacopo Mondi > > --- > > > > drivers/gpu/drm/bridge/thc63lvd1024.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c > > b/drivers/gpu/drm/bridge/thc63lvd1024.c index c8b9edd5a7f4..63609ba16b6d > > 100644 > > --- a/drivers/gpu/drm/bridge/thc63lvd1024.c > > +++ b/drivers/gpu/drm/bridge/thc63lvd1024.c > > @@ -45,6 +45,23 @@ static int thc63_attach(struct drm_bridge *bridge) > > return drm_bridge_attach(bridge->encoder, thc63->next, bridge); > > } > > > > +static enum drm_mode_status thc63_mode_valid(struct drm_bridge *bridge, > > + const struct drm_display_mode *mode) > > +{ > > + /* > > + * The THC63LVD0124 clock frequency range is 8 to 135 MHz in single-in, > > That should be THC63LVD1024. Will be fixed in v3. > > + * single-out mode. > > For the input clock (that's what we're talking about, right?), that also > applies to single-in/dual-out. Maybe just omit the "single-out" clause? Good point, I'll change that in v3. > > Note that the limits depends on the mode and will > > + * need to be adjusted accordingly. > > + */ > > I don't quite understand. Does that refer to the THC63 mode, or the DRM > mode? This refers to the THC63 mode, I'll clarify this in v3 as well. > > + if (mode->clock < 8000) > > + return MODE_CLOCK_LOW; > > + > > + if (mode->clock > 135000) > > + return MODE_CLOCK_HIGH; > > + > > + return MODE_OK; > > +} > > + > > static void thc63_enable(struct drm_bridge *bridge) > > { > > struct thc63_dev *thc63 = to_thc63(bridge); > > @@ -77,6 +94,7 @@ static void thc63_disable(struct drm_bridge *bridge) > > > > static const struct drm_bridge_funcs thc63_bridge_func = { > > .attach = thc63_attach, > > + .mode_valid = thc63_mode_valid, > > .enable = thc63_enable, > > .disable = thc63_disable, > > }; -- Regards, Laurent Pinchart