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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1755119192; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LXUYdiyOFdWb2xcTIWDWLT2Bvo7KGxD/FsHoRDWMjLQ=; b=NuBoddv9AmQnPes2jc96mrnsseP+r/5e9ocN8z9av21vKWoJzMeY16g6hn867p1gLz02L9 0r9F6E1vp46jzcQ02gA/5UmLrxTRIMrQ3QihBEVRkIGy4b0achV8a2HPaVk2L2KzbNLRcx XFyeN/7ZNJFdmWRcHfNcdpq+VnOFcNWHANtDo7IESjT3cq7BaX43BDstVmYm71XZUiERtE XsjDXrUVOliJELUOESeXh0c5GoBcyR0nTTlmHpqhTRqr7mcwAqzXJFeeHAaSY8Nh6SvGKU jBSZ9TIFLsVUhwvjc37jyENQIYNs4AraOVWHFEoIym/do7XVAsJ6R/uVhwiWeA== Date: Wed, 13 Aug 2025 23:06:29 +0200 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH 2/4] drm/rcar-du: dsi: Remove fixed PPI lane count setup To: Tomi Valkeinen , Marek Vasut , dri-devel@lists.freedesktop.org Cc: David Airlie , Geert Uytterhoeven , Kieran Bingham , Laurent Pinchart , Maarten Lankhorst , Magnus Damm , Maxime Ripard , Simona Vetter , Thomas Zimmermann , linux-renesas-soc@vger.kernel.org References: <20250608142636.54033-1-marek.vasut+renesas@mailbox.org> <20250608142636.54033-3-marek.vasut+renesas@mailbox.org> <64b49da6-15ae-45e1-a4af-c1f08f80cf3a@ideasonboard.com> <87cc32a7-fe1d-4d8d-b793-e3bb7e12fb7d@ideasonboard.com> <1ae735be-3d07-4520-8013-c4b7a1b1c26a@mailbox.org> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-MBO-RS-META: b8gk49p5fhsj1kx4fjuty8it7smzhqd3 X-MBO-RS-ID: 5623dcfe4c04eeb44dd X-Rspamd-Queue-Id: 4c2LXB3dC4z9t9l On 8/13/25 9:34 AM, Tomi Valkeinen wrote: Hi, >>>>> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/ >>>>> drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >>>>> index b3e57217ae63..cefa7e92b5b8 100644 >>>>> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >>>>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >>>>> @@ -80,10 +80,7 @@ >>>>>    * PHY-Protocol Interface (PPI) Registers >>>>>    */ >>>>>   #define PPISETR                0x700 >>>>> -#define PPISETR_DLEN_0            (0x1 << 0) >>>>> -#define PPISETR_DLEN_1            (0x3 << 0) >>>>> -#define PPISETR_DLEN_2            (0x7 << 0) >>>>> -#define PPISETR_DLEN_3            (0xf << 0) >>>>> +#define PPISETR_DLEN_MASK        (0xf << 0) >>>>>   #define PPISETR_CLEN            BIT(8) >>>> >>>> Looks fine, but do you know what the TXSETR register does? It also has >>>> LANECNT, but I don't see the driver touching that register at all. >>>> TXSETR:LANECNT default value is 3 (4 lanes), which matches with the old >>>> hardcoded behavior for PPISETR... So I wonder if that register should >>>> also be set? >>> >>> Ah, never mind, I now saw the patch 3 =). But should it be before patch >>> 2? Hmm, I guess that ordering is no better. Should they be combined into >>> "support 1,2,3 datalanes" patch? >> I think each patch fixes slighly different issue, even if the issues are >> related. I tried to keep the issue description in each patch commit >> message for posterity. I can squash them if you think that's better, I >> don't mind either way. > > I was thinking about this the user's or backporting point of view. > Neither of the commits (clearly) say that they add support for 1/2/3 > lane modes. The 1/2/3 lane mode was already implemented in the driver, except it was broken. > You say they "fix", but they're not quite fixes either. The > patch 3 could be considered a fix, but at the moment it just writes the > default value to the register, so no point in marking it as a fix to be > backported. 3/4 does write the DSI lane count into TXSETR , not the default value. > So... I don't have a strong opinion, but I think a single patch that > adds support to 1, 2,3 lanes makes most sense. Lemme send a single patch with Fixes tag then. The combined patch does not look too great though.