RE: [PATCH 3/3] irqchip/renesas-rzg2l: Add NMI support

Thomas Gleixner
2026-03-31T20:29:49Z

On Tue, Mar 31 2026 at 17:10, Biju Das wrote:
>> From: Thomas Gleixner <tglx@kernel.org>
> Will drop the lock as it is not RMW operation.

Huch?

> +static void rzg2l_clear_nmi_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> +{
> + u32 bit = BIT(hwirq);
> + u32 reg;
> +
> + reg = readl_relaxed(priv->base + NSCR);
> + if (reg & bit) {
> + writel_relaxed(reg & ~bit, priv->base + NSCR);
> + /*
> + * Enforce that the posted write is flushed to prevent that the
> + * just handled interrupt is raised again.
> + */
> + readl_relaxed(priv->base + NSCR);
> + }
> +}

How is that not RMW?

I assume that you want to explain that it's not a RMW on a shared
register, right?

Thanks,

tglx