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Fri, 01 Aug 2025 04:15:48 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250729155915.67758-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250729155915.67758-9-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 1 Aug 2025 12:15:22 +0100 X-Gm-Features: Ac12FXxB7KTWna_KgkuQC2HTkAPiZxLfvyASMmBcJptTa4JiUTiZzqkfcolFBD4 Message-ID: Subject: Re: [PATCH v2 8/9] watchdog: rzv2h: Add support for RZ/T2H To: Wolfram Sang Cc: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Wolfram, Thank you for the review. On Fri, Aug 1, 2025 at 5:12=E2=80=AFAM Wolfram Sang wrote: > > On Tue, Jul 29, 2025 at 04:59:14PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Add support for the RZ/T2H watchdog timer. The RZ/T2H requires control = of > > the watchdog counter using the WDT Debug Control Register (WDTDCR), whi= ch > > allows explicitly stopping and starting the counter. This behavior diff= ers > > from RZ/V2H, which doesn't use WDTDCR, so the driver is extended to han= dle > > this requirement. > > Is it really required or is it an additional feature? > Sorry for not being clear WDTDCR register is not present on the RZ/V2H(P) SoC, and is required on RZ/T2H (and RZ/N2H) SoC to start/stop down counting. > > To support this, a new `wdtdcr` flag is introduced in the `rzv2h_of_dat= a` > > structure. When set, the driver maps the WDTDCR register and uses it to > > control the watchdog counter in the start, stop, and restart callbacks. > > Additionally, the clock divisor and count source for RZ/T2H are defined > > to match its hardware configuration. > > Where is the register placed? We need a seperate resource for it? Can > you kindly give an example DT node for this case? > The WDTDCR register is placed somewhere out and yes we need a separate resource for it. Below is the node for RZ/T2H SoC: wdt0: watchdog@80082000 { compatible =3D "renesas,r9a09g077-wdt"; reg =3D <0 0x80082000 0 0x400>, <0 0x81295100 0 0x04>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; status =3D "disabled"; }; Cheers, Prabhakar