From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 2/3] clk: renesas: r9a09g077-cpg: Add PLL2 and SDHI clock support
Date: Wed, 2 Jul 2025 15:38:14 +0200 [thread overview]
Message-ID: <CAMuHMdVpc2asQpmYjhGT3iyu1t8RUtSGNivugncWpK9dmk+VjQ@mail.gmail.com> (raw)
In-Reply-To: <20250625141705.151383-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
> register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
> operating at 800MHz.
>
> Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
> module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
> clock source.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2025-07-02 13:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-25 14:17 [PATCH 0/3] clk: renesas: Add SDHI and RIIC clock support for RZ/T2H and RZ/N2H Prabhakar
2025-06-25 14:17 ` [PATCH 1/3] dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID Prabhakar
2025-07-02 13:37 ` Geert Uytterhoeven
2025-07-02 18:23 ` Geert Uytterhoeven
2025-07-02 19:27 ` Lad, Prabhakar
2025-06-25 14:17 ` [PATCH 2/3] clk: renesas: r9a09g077-cpg: Add PLL2 and SDHI clock support Prabhakar
2025-07-02 13:38 ` Geert Uytterhoeven [this message]
2025-06-25 14:17 ` [PATCH 3/3] clk: renesas: r9a09g077-cpg: Add RIIC module clocks Prabhakar
2025-07-02 13:46 ` Geert Uytterhoeven
2025-07-02 19:30 ` Lad, Prabhakar
2025-07-02 19:37 ` Geert Uytterhoeven
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