Re: [PATCH 2/3] pinctrl: renesas: Initial R8A779A0 (V3U) PFC support

[Geert Uytterhoeven <geert@linux-m68k.org>]

Hi Uli,

One more comment...

On Thu, Nov 26, 2020 at 6:21 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
> including bias control.

... and drive strength, and I/O voltage control.

> + static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
> +                                    u32 *pocctrl)
> + {
> +         int bit = pin & 0x1f;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC0].reg;
> +         if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC1].reg;
> +         if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC2].reg;
> +         if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
> +                 return bit;

The above are pins switchable between 1.8V and 3.3V pins, which are
handled fine.

> +
> +         *pocctrl = pinmux_ioctrl_regs[POC4].reg;
> +         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC5].reg;
> +         if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC6].reg;
> +         if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC7].reg;
> +         if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC8].reg;
> +         if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
> +                 return bit;
> +
> +         *pocctrl = pinmux_ioctrl_regs[POC9].reg;
> +         if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
> +                 return bit;

The above are 2.5/3.3V pins, and they are not handled correctly by
sh_pfc_pinconf_[gs]et(), which always assumes 1.8/3.3V.

I think the simplest solution would be to split the
SH_PFC_PIN_CFG_IO_VOLTAGE flag in two flags, and the pin_to_pocctrl()
callback in two callbacks, one for 1.8/3.3V and one for 2.5/3.3V pins,
but you may have a better idea?

Note that the R-Car V3M, V3H, E3, and D3 SoCs also have 2.5/3.3V pins,
but their pinctrl drivers just don't handle them, and limit voltage control
to the 1.8/3.3V pins.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds