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From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 2/2] reset: rzg2l-usbphy-ctrl: Add suspend/resume support
Date: Fri, 7 Nov 2025 15:57:02 +0200	[thread overview]
Message-ID: <a7f28253-b4c4-4965-a292-e4ab9dcc7f81@tuxon.dev> (raw)
In-Reply-To: <575b271790b267ac4cbbb190b26341656e2c7e0c.camel@pengutronix.de>

Hi, Philipp,

On 11/7/25 15:50, Philipp Zabel wrote:
> On Do, 2025-11-06 at 16:33 +0200, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The RZ/G2L USBPHY control driver is also used on the RZ/G3S SoC.
>> The RZ/G3S SoC supports a power-saving mode in which power to most USB
>> components (including the USBPHY control block) is turned off. Because of
>> this, the USBPHY control block needs to be reconfigured when returning
>> from power-saving mode.
>>
>> Add suspend/resume support to handle runtime suspend/resume of the device,
>> assert/deassert the reset signal, and reinitialize the USBPHY control
>> block.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  drivers/reset/reset-rzg2l-usbphy-ctrl.c | 94 +++++++++++++++++++++----
>>  1 file changed, 79 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
>> index 9ce0c1f5d465..8ba65839f6e4 100644
>> --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
>> +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> [...]
>> @@ -266,10 +273,67 @@ static void rzg2l_usbphy_ctrl_remove(struct platform_device *pdev)
>>  	reset_control_assert(priv->rstc);
>>  }
>>  
>> +static int rzg2l_usbphy_ctrl_suspend(struct device *dev)
>> +{
>> +	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev);
>> +	int ret;
>> +
>> +	pm_runtime_put(dev);
> 
> Should this be pm_runtime_put_sync(dev)?
> 
>> +
>> +	ret = reset_control_assert(priv->rstc);
>> +	if (ret)
>> +		goto rpm_resume;
>> +
>> +	ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false);
> 
> This sets PWRRDY=1, and needs to be set after MSTOP=1,CLK_ON=0,
> according to 58128aa88867 ("reset: rzg2l-usbphy-ctrl: Add support for
> USB PWRRDY"). I assume MSTOP/CLK_ON refer to the PHY clock in that
> description,

It refers to the MSTOP/CLK_ON of the USB block. USB PHY CTRL and USB PHYs
are all part of the USB block.

> so the pm_runtime_put() above is required to have taken
> effect here.

You're right. I'll use pm_runtime_put_sync().

Thank you for your review,
Claudiu

      reply	other threads:[~2025-11-07 13:57 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-06 14:33 [PATCH 0/2] reset: rzg2l-usbphy-ctrl: Add suspend to RAM support Claudiu
2025-11-06 14:33 ` [PATCH 1/2] reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits() Claudiu
2025-11-07 13:25   ` Philipp Zabel
2025-11-06 14:33 ` [PATCH 2/2] reset: rzg2l-usbphy-ctrl: Add suspend/resume support Claudiu
2025-11-07 13:50   ` Philipp Zabel
2025-11-07 13:57     ` Claudiu Beznea [this message]

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