[PATCH 00/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[PATCH 00/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Brian Masney]

There are some clocks where the rounding is managed by the hardware, and
the determine_rate() clk ops is just a noop that simply returns 0. Based
on discussions with Stephen at Linux Plumbers Conference, he suggested
adding a flag for this particular case. So let's add a new flag, and
update the clk core so that the determine_rate() clk op is not required
when this flag is set.
    
This series adds the flag, some kunit tests, and updates all of the
relevant drivers under drivers/clk to use the new flag.
    
Once this is merged, and in Linus's tree, I can update the few remaining
clk drivers that are outside of drivers/clk via those subsystems at a
later time.

Merge Strategy
--------------
All of this needs to be directly merged by Stephen as one series into
his tree. Subsystem maintainers: please leave a Reviewed-by or Acked-by.
To reduce the noise, I am only CCing people on their respective drivers.

Note this series depends on 3 previously-posted patches in this git pull
to Stephen for v7.1.
https://lore.kernel.org/linux-clk/aZuK4-QJCXUeSxtL@redhat.com/
Hopefully I set the depeendencies up correctly in b4.

Signed-off-by: Brian Masney <bmasney@redhat.com>
---
Brian Masney (13):
      clk: add new flag CLK_ROUNDING_FW_MANAGED
      clk: test: add test suite for CLK_ROUNDING_FW_MANAGED flag
      clk: rp1: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: scpi: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: hisilicon: hi3660-stub: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: imx: scu: drop redundant init.ops variable assignment
      clk: imx: scu: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: qcom: rpm: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: qcom: rpmh: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: qcom: smd-rpm: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: samsung: acpm: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
      clk: sprd: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

 drivers/clk/clk-rp1.c                   | 11 +----
 drivers/clk/clk-scpi.c                  | 14 +-----
 drivers/clk/clk.c                       | 24 ++++++++--
 drivers/clk/clk_test.c                  | 85 +++++++++++++++++++++++++++++++++
 drivers/clk/hisilicon/clk-hi3660-stub.c | 14 +-----
 drivers/clk/imx/clk-scu.c               | 23 +--------
 drivers/clk/qcom/clk-rpm.c              | 16 ++-----
 drivers/clk/qcom/clk-rpmh.c             |  8 +---
 drivers/clk/qcom/clk-smd-rpm.c          | 15 +-----
 drivers/clk/renesas/rzg2l-cpg.c         |  9 +---
 drivers/clk/samsung/clk-acpm.c          | 14 +-----
 drivers/clk/sprd/pll.c                  |  7 ---
 drivers/clk/sprd/pll.h                  |  2 +-
 include/linux/clk-provider.h            |  2 +
 14 files changed, 123 insertions(+), 121 deletions(-)
---
base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
change-id: 20260226-clk-det-rate-fw-managed-4b8d061f31be
prerequisite-patch-id: 59198edc95aca82a29327137ad2af82ec13295b6
prerequisite-patch-id: 8932e170649711d7a80c57784033a37faadd519b
prerequisite-patch-id: 91c7b1851c5d77e504c49ce6bf14b3f8b84e826a

Best regards,
-- 
Brian Masney <bmasney@redhat.com>

[PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Brian Masney]

There are some clocks where the rounding is managed by the hardware, and
the determine_rate() clk ops is just a noop that simply returns 0. Add a
new flag for these type of clocks, and update the clk core so that the
determine_rate() clk op is not required when this flag is set.

Signed-off-by: Brian Masney <bmasney@redhat.com>

---
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Abel Vesa <abelvesa@kernel.org>
To: Andrea della Porta <andrea.porta@suse.com>
To: Baolin Wang <baolin.wang@linux.alibaba.com>
To: Bjorn Andersson <andersson@kernel.org>
To: Chanwoo Choi <cw00.choi@samsung.com>
To: Frank Li <Frank.Li@nxp.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
To: Krzysztof Kozlowski <krzk@kernel.org>
To: Orson Zhai <orsonzhai@gmail.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
To: Sudeep Holla <sudeep.holla@kernel.org>
To: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: arm-scmi@vger.kernel.org
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Cc: Cristian Marussi <cristian.marussi@arm.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
---
 drivers/clk/clk.c            | 24 +++++++++++++++++++++---
 include/linux/clk-provider.h |  2 ++
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index fd418dc988b1c60c49e3ac9c0c44aa132dd5da28..0a522a0817411c7f7c6e9cffd6f024e672a331a8 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1557,6 +1557,20 @@ static int __init clk_disable_unused(void)
 }
 late_initcall_sync(clk_disable_unused);
 
+/**
+ * clk_is_rounding_fw_managed - Check to see if clk rounding is handled by the
+ * firmware.
+ * @core: the clk to check
+ *
+ * Clks that have this flag enabled do not need to have a determine_rate() op
+ * set, and will always return success for any rounding operation since the
+ * firmware will deal with the rounding.
+ */
+static inline bool clk_is_rounding_fw_managed(struct clk_core *core)
+{
+	return core->flags & CLK_ROUNDING_FW_MANAGED;
+}
+
 static int clk_core_determine_round_nolock(struct clk_core *core,
 					   struct clk_rate_request *req)
 {
@@ -1589,6 +1603,8 @@ static int clk_core_determine_round_nolock(struct clk_core *core,
 		req->rate = core->rate;
 	} else if (core->ops->determine_rate) {
 		return core->ops->determine_rate(core->hw, req);
+	} else if (clk_is_rounding_fw_managed(core)) {
+		return 0;
 	} else {
 		return -EINVAL;
 	}
@@ -1673,7 +1689,7 @@ EXPORT_SYMBOL_GPL(clk_hw_forward_rate_request);
 
 static bool clk_core_can_round(struct clk_core * const core)
 {
-	return core->ops->determine_rate;
+	return core->ops->determine_rate || clk_is_rounding_fw_managed(core);
 }
 
 static int clk_core_round_rate_nolock(struct clk_core *core,
@@ -3528,6 +3544,7 @@ static const struct {
 	ENTRY(CLK_IS_CRITICAL),
 	ENTRY(CLK_OPS_PARENT_ENABLE),
 	ENTRY(CLK_DUTY_CYCLE_PARENT),
+	ENTRY(CLK_ROUNDING_FW_MANAGED),
 #undef ENTRY
 };
 
@@ -3906,7 +3923,7 @@ static int __clk_core_init(struct clk_core *core)
 
 	/* check that clk_ops are sane.  See Documentation/driver-api/clk.rst */
 	if (core->ops->set_rate && !core->ops->determine_rate &&
-	      core->ops->recalc_rate) {
+	      core->ops->recalc_rate && !clk_is_rounding_fw_managed(core)) {
 		pr_err("%s: %s must implement .determine_rate in addition to .recalc_rate\n",
 		       __func__, core->name);
 		ret = -EINVAL;
@@ -3920,7 +3937,8 @@ static int __clk_core_init(struct clk_core *core)
 		goto out;
 	}
 
-	if (core->ops->set_parent && !core->ops->determine_rate) {
+	if (core->ops->set_parent && !core->ops->determine_rate &&
+	    !clk_is_rounding_fw_managed(core)) {
 		pr_err("%s: %s must implement .set_parent & .determine_rate\n",
 			__func__, core->name);
 		ret = -EINVAL;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1cda2c78dffaff037f0f16b0f11106b63b3a746f..187f8248a9c840c701cbbba99bb7cdeef7b654ee 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -32,6 +32,8 @@
 #define CLK_OPS_PARENT_ENABLE	BIT(12)
 /* duty cycle call may be forwarded to the parent clock */
 #define CLK_DUTY_CYCLE_PARENT	BIT(13)
+/* clock rate rounding is managed by firmware, don't require determine_rate */
+#define CLK_ROUNDING_FW_MANAGED		BIT(14)
 
 struct clk;
 struct clk_hw;

-- 
2.53.0

[PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Brian Masney]

This clk driver has a noop determine_rate clk op. Drop this empty
function, and enable the CLK_ROUNDING_FW_MANAGED flag.

Signed-off-by: Brian Masney <bmasney@redhat.com>

---
To: Geert Uytterhoeven <geert+renesas@glider.be>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/clk/renesas/rzg2l-cpg.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c0584bab58a3ba8a637e77662191f89a57bf1390..126398267e60d1f0fa7ababcb22a5c540884e810 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
 	return pll5_rate;
 }
 
-static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
-					   struct clk_rate_request *req)
-{
-	return 0;
-}
-
 static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
 				     unsigned long rate,
 				     unsigned long parent_rate)
@@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
 
 static const struct clk_ops rzg2l_cpg_sipll5_ops = {
 	.recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
-	.determine_rate = rzg2l_cpg_sipll5_determine_rate,
 	.set_rate = rzg2l_cpg_sipll5_set_rate,
 };
 
@@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
 	init.name = core->name;
 	parent_name = __clk_get_name(parent);
 	init.ops = &rzg2l_cpg_sipll5_ops;
-	init.flags = 0;
+	init.flags = CLK_ROUNDING_FW_MANAGED;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 

-- 
2.53.0

Re: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Geert Uytterhoeven]

Hi Brian,

Thanks for your patch!

On Thu, 26 Feb 2026 at 19:17, Brian Masney <bmasney@redhat.com> wrote:
> There are some clocks where the rounding is managed by the hardware, and

s/hardware/firmware/

You got me totally confused, also/especially in the cover letter! ;-)

> the determine_rate() clk ops is just a noop that simply returns 0. Add a
> new flag for these type of clocks, and update the clk core so that the
> determine_rate() clk op is not required when this flag is set.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Geert Uytterhoeven]

Hi Brian,

C Biju

On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> This clk driver has a noop determine_rate clk op. Drop this empty
> function, and enable the CLK_ROUNDING_FW_MANAGED flag.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
>         return pll5_rate;
>  }
>
> -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
> -                                          struct clk_rate_request *req)
> -{
> -       return 0;
> -}
> -
>  static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
>                                      unsigned long rate,
>                                      unsigned long parent_rate)
> @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
>
>  static const struct clk_ops rzg2l_cpg_sipll5_ops = {
>         .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
> -       .determine_rate = rzg2l_cpg_sipll5_determine_rate,
>         .set_rate = rzg2l_cpg_sipll5_set_rate,
>  };
>
> @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
>         init.name = core->name;
>         parent_name = __clk_get_name(parent);
>         init.ops = &rzg2l_cpg_sipll5_ops;
> -       init.flags = 0;
> +       init.flags = CLK_ROUNDING_FW_MANAGED;

Iff this is the Right Thing To Do (TM), it needs a comment, as this
clock is not managed by firmware.

>         init.parent_names = &parent_name;
>         init.num_parents = 1;
>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Biju Das]

Thanks, I will test and provide the feedback.

Cheers,
Biju

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On Behalf Of Geert Uytterhoeven
> Sent: 27 February 2026 08:17
> Subject: Re: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED
> 
> Hi Brian,
> 
> Thanks for your patch!
> 
> On Thu, 26 Feb 2026 at 19:17, Brian Masney <bmasney@redhat.com> wrote:
> > There are some clocks where the rounding is managed by the hardware,
> > and
> 
> s/hardware/firmware/
> 
> You got me totally confused, also/especially in the cover letter! ;-)
> 
> > the determine_rate() clk ops is just a noop that simply returns 0. Add
> > a new flag for these type of clocks, and update the clk core so that
> > the
> > determine_rate() clk op is not required when this flag is set.
> >
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

RE: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Biju Das]

Hi Brain,

Thanks for the patch

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On Behalf Of Brian Masney
> Sent: 26 February 2026 18:17
> Subject: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED
> 
> There are some clocks where the rounding is managed by the hardware, and the determine_rate() clk ops
> is just a noop that simply returns 0. Add a new flag for these type of clocks, and update the clk core
> so that the
> determine_rate() clk op is not required when this flag is set.
> 
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> 
> ---
> To: Michael Turquette <mturquette@baylibre.com>
> To: Stephen Boyd <sboyd@kernel.org>
> To: Abel Vesa <abelvesa@kernel.org>
> To: Andrea della Porta <andrea.porta@suse.com>
> To: Baolin Wang <baolin.wang@linux.alibaba.com>
> To: Bjorn Andersson <andersson@kernel.org>
> To: Chanwoo Choi <cw00.choi@samsung.com>
> To: Frank Li <Frank.Li@nxp.com>
> To: Geert Uytterhoeven <geert+renesas@glider.be>
> To: Krzysztof Kozlowski <krzk@kernel.org>
> To: Orson Zhai <orsonzhai@gmail.com>
> To: Sascha Hauer <s.hauer@pengutronix.de>
> To: Sudeep Holla <sudeep.holla@kernel.org>
> To: Sylwester Nawrocki <s.nawrocki@samsung.com>
> To: Tudor Ambarus <tudor.ambarus@linaro.org>
> Cc: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: arm-scmi@vger.kernel.org
> Cc: Chunyan Zhang <zhang.lyra@gmail.com>
> Cc: Cristian Marussi <cristian.marussi@arm.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: imx@lists.linux.dev
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> Cc: linux-samsung-soc@vger.kernel.org
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> ---
>  drivers/clk/clk.c            | 24 +++++++++++++++++++++---
>  include/linux/clk-provider.h |  2 ++
>  2 files changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index
> fd418dc988b1c60c49e3ac9c0c44aa132dd5da28..0a522a0817411c7f7c6e9cffd6f024e672a331a8 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1557,6 +1557,20 @@ static int __init clk_disable_unused(void)  }
> late_initcall_sync(clk_disable_unused);
> 
> +/**
> + * clk_is_rounding_fw_managed - Check to see if clk rounding is handled
> +by the
> + * firmware.
> + * @core: the clk to check
> + *
> + * Clks that have this flag enabled do not need to have a
> +determine_rate() op
> + * set, and will always return success for any rounding operation since
> +the
> + * firmware will deal with the rounding.
> + */
> +static inline bool clk_is_rounding_fw_managed(struct clk_core *core) {
> +	return core->flags & CLK_ROUNDING_FW_MANAGED; }
> +
>  static int clk_core_determine_round_nolock(struct clk_core *core,
>  					   struct clk_rate_request *req)
>  {
> @@ -1589,6 +1603,8 @@ static int clk_core_determine_round_nolock(struct clk_core *core,
>  		req->rate = core->rate;
>  	} else if (core->ops->determine_rate) {
>  		return core->ops->determine_rate(core->hw, req);
> +	} else if (clk_is_rounding_fw_managed(core)) {
> +		return 0;
>  	} else {
>  		return -EINVAL;
>  	}
> @@ -1673,7 +1689,7 @@ EXPORT_SYMBOL_GPL(clk_hw_forward_rate_request);
> 
>  static bool clk_core_can_round(struct clk_core * const core)  {
> -	return core->ops->determine_rate;
> +	return core->ops->determine_rate || clk_is_rounding_fw_managed(core);
>  }
> 
>  static int clk_core_round_rate_nolock(struct clk_core *core, @@ -3528,6 +3544,7 @@ static const
> struct {
>  	ENTRY(CLK_IS_CRITICAL),
>  	ENTRY(CLK_OPS_PARENT_ENABLE),
>  	ENTRY(CLK_DUTY_CYCLE_PARENT),
> +	ENTRY(CLK_ROUNDING_FW_MANAGED),
>  #undef ENTRY
>  };
> 
> @@ -3906,7 +3923,7 @@ static int __clk_core_init(struct clk_core *core)
> 
>  	/* check that clk_ops are sane.  See Documentation/driver-api/clk.rst */
>  	if (core->ops->set_rate && !core->ops->determine_rate &&
> -	      core->ops->recalc_rate) {
> +	      core->ops->recalc_rate && !clk_is_rounding_fw_managed(core)) {
>  		pr_err("%s: %s must implement .determine_rate in addition to .recalc_rate\n",
>  		       __func__, core->name);
>  		ret = -EINVAL;
> @@ -3920,7 +3937,8 @@ static int __clk_core_init(struct clk_core *core)
>  		goto out;
>  	}
> 
> -	if (core->ops->set_parent && !core->ops->determine_rate) {
> +	if (core->ops->set_parent && !core->ops->determine_rate &&
> +	    !clk_is_rounding_fw_managed(core)) {

>  		pr_err("%s: %s must implement .set_parent & .determine_rate\n",
>  			__func__, core->name);
>  		ret = -EINVAL;


After applying patch#11, I get a message as you removed .determine_rate, Also it breaks display.

[    0.096414] __clk_core_init: .pll5_foutpostdiv must implement .round_rate or .determine_rate in addition to .recalc_rate


Cheers,
Biju

Re: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Brian Masney]

On Fri, Feb 27, 2026 at 12:00:55PM +0000, Biju Das wrote:
> > -----Original Message-----
> > From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On Behalf Of Brian Masney
> > Sent: 26 February 2026 18:17
> > Subject: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED
> > 
> > There are some clocks where the rounding is managed by the hardware, and the determine_rate() clk ops
> > is just a noop that simply returns 0. Add a new flag for these type of clocks, and update the clk core
> > so that the
> > determine_rate() clk op is not required when this flag is set.
> > 
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > 
[snip]
> >  drivers/clk/clk.c            | 24 +++++++++++++++++++++---
> >  include/linux/clk-provider.h |  2 ++
> >  2 files changed, 23 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index
> > fd418dc988b1c60c49e3ac9c0c44aa132dd5da28..0a522a0817411c7f7c6e9cffd6f024e672a331a8 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -1557,6 +1557,20 @@ static int __init clk_disable_unused(void)  }
> > late_initcall_sync(clk_disable_unused);
> > 
> > +/**
> > + * clk_is_rounding_fw_managed - Check to see if clk rounding is handled
> > +by the
> > + * firmware.
> > + * @core: the clk to check
> > + *
> > + * Clks that have this flag enabled do not need to have a
> > +determine_rate() op
> > + * set, and will always return success for any rounding operation since
> > +the
> > + * firmware will deal with the rounding.
> > + */
> > +static inline bool clk_is_rounding_fw_managed(struct clk_core *core) {
> > +	return core->flags & CLK_ROUNDING_FW_MANAGED; }
> > +
> >  static int clk_core_determine_round_nolock(struct clk_core *core,
> >  					   struct clk_rate_request *req)
> >  {
> > @@ -1589,6 +1603,8 @@ static int clk_core_determine_round_nolock(struct clk_core *core,
> >  		req->rate = core->rate;
> >  	} else if (core->ops->determine_rate) {
> >  		return core->ops->determine_rate(core->hw, req);
> > +	} else if (clk_is_rounding_fw_managed(core)) {
> > +		return 0;
> >  	} else {
> >  		return -EINVAL;
> >  	}
> > @@ -1673,7 +1689,7 @@ EXPORT_SYMBOL_GPL(clk_hw_forward_rate_request);
> > 
> >  static bool clk_core_can_round(struct clk_core * const core)  {
> > -	return core->ops->determine_rate;
> > +	return core->ops->determine_rate || clk_is_rounding_fw_managed(core);
> >  }
> > 
> >  static int clk_core_round_rate_nolock(struct clk_core *core, @@ -3528,6 +3544,7 @@ static const
> > struct {
> >  	ENTRY(CLK_IS_CRITICAL),
> >  	ENTRY(CLK_OPS_PARENT_ENABLE),
> >  	ENTRY(CLK_DUTY_CYCLE_PARENT),
> > +	ENTRY(CLK_ROUNDING_FW_MANAGED),
> >  #undef ENTRY
> >  };
> > 
> > @@ -3906,7 +3923,7 @@ static int __clk_core_init(struct clk_core *core)
> > 
> >  	/* check that clk_ops are sane.  See Documentation/driver-api/clk.rst */
> >  	if (core->ops->set_rate && !core->ops->determine_rate &&
> > -	      core->ops->recalc_rate) {
> > +	      core->ops->recalc_rate && !clk_is_rounding_fw_managed(core)) {
> >  		pr_err("%s: %s must implement .determine_rate in addition to .recalc_rate\n",
> >  		       __func__, core->name);
> >  		ret = -EINVAL;
> > @@ -3920,7 +3937,8 @@ static int __clk_core_init(struct clk_core *core)
> >  		goto out;
> >  	}
> > 
> > -	if (core->ops->set_parent && !core->ops->determine_rate) {
> > +	if (core->ops->set_parent && !core->ops->determine_rate &&
> > +	    !clk_is_rounding_fw_managed(core)) {
> 
> >  		pr_err("%s: %s must implement .set_parent & .determine_rate\n",
> >  			__func__, core->name);
> >  		ret = -EINVAL;
> 
> 
> After applying patch#11, I get a message as you removed .determine_rate, Also it breaks display.
> 
> [    0.096414] __clk_core_init: .pll5_foutpostdiv must implement .round_rate or .determine_rate in addition to .recalc_rate

Thanks for testing. This happens because rzg2l_cpg_pll_clk_register()
doesn't have the new flag set. I'll fix this, and go through all of the
others again just to make sure I don't miss any others.

Brian

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Brian Masney]

On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > This clk driver has a noop determine_rate clk op. Drop this empty
> > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> >
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> >         return pll5_rate;
> >  }
> >
> > -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
> > -                                          struct clk_rate_request *req)
> > -{
> > -       return 0;
> > -}
> > -
> >  static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> >                                      unsigned long rate,
> >                                      unsigned long parent_rate)
> > @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> >
> >  static const struct clk_ops rzg2l_cpg_sipll5_ops = {
> >         .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
> > -       .determine_rate = rzg2l_cpg_sipll5_determine_rate,
> >         .set_rate = rzg2l_cpg_sipll5_set_rate,
> >  };
> >
> > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> >         init.name = core->name;
> >         parent_name = __clk_get_name(parent);
> >         init.ops = &rzg2l_cpg_sipll5_ops;
> > -       init.flags = 0;
> > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> 
> Iff this is the Right Thing To Do (TM), it needs a comment, as this
> clock is not managed by firmware.

It needs a better name for the flag. I'll reply on patch 1 where more
people are CCed to see if we can come up with a better idea.

Brian

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Brian Masney]

Hi Geert,

On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > This clk driver has a noop determine_rate clk op. Drop this empty
> > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> >
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> >         return pll5_rate;
> >  }
> >
> > -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
> > -                                          struct clk_rate_request *req)
> > -{
> > -       return 0;
> > -}
> > -
> >  static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> >                                      unsigned long rate,
> >                                      unsigned long parent_rate)
> > @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> >
> >  static const struct clk_ops rzg2l_cpg_sipll5_ops = {
> >         .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
> > -       .determine_rate = rzg2l_cpg_sipll5_determine_rate,
> >         .set_rate = rzg2l_cpg_sipll5_set_rate,
> >  };
> >
> > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> >         init.name = core->name;
> >         parent_name = __clk_get_name(parent);
> >         init.ops = &rzg2l_cpg_sipll5_ops;
> > -       init.flags = 0;
> > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> 
> Iff this is the Right Thing To Do (TM), it needs a comment, as this
> clock is not managed by firmware.

Before I start a larger discussion on patch 1 with more people about a
name for this flag, help me understand why this provider has a noop
determine rate. Is the hardware eventually programmed with a rate
that's close enough to what was passed in? Or it doesn't really matter
what the clock rate is, just as long as it is running? Or should the
determine_rate function be filled out in this particular case?

Thanks,

Brian

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Geert Uytterhoeven]

Hi Brian,

On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > This clk driver has a noop determine_rate clk op. Drop this empty
> > > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > >
> > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > +++ b/drivers/clk/renesas/rzg2l-cpg.c

> > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > >         init.name = core->name;
> > >         parent_name = __clk_get_name(parent);
> > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > -       init.flags = 0;
> > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> >
> > Iff this is the Right Thing To Do (TM), it needs a comment, as this
> > clock is not managed by firmware.
>
> Before I start a larger discussion on patch 1 with more people about a
> name for this flag, help me understand why this provider has a noop
> determine rate. Is the hardware eventually programmed with a rate
> that's close enough to what was passed in? Or it doesn't really matter
> what the clock rate is, just as long as it is running? Or should the
> determine_rate function be filled out in this particular case?

I'd like to defer to Biju, who added the empty round^Wdetermine rate
function.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Biju Das]

Hi Brian/Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 27 February 2026 15:09
> Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use
> CLK_ROUNDING_FW_MANAGED flag
> 
> Hi Brian,
> 
> On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> > On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > > This clk driver has a noop determine_rate clk op. Drop this empty
> > > > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > > >
> > > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> 
> > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > >         init.name = core->name;
> > > >         parent_name = __clk_get_name(parent);
> > > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > > -       init.flags = 0;
> > > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> > >
> > > Iff this is the Right Thing To Do (TM), it needs a comment, as this
> > > clock is not managed by firmware.
> >
> > Before I start a larger discussion on patch 1 with more people about a
> > name for this flag, help me understand why this provider has a noop
> > determine rate. Is the hardware eventually programmed with a rate
> > that's close enough to what was passed in? Or it doesn't really matter
> > what the clock rate is, just as long as it is running? Or should the
> > determine_rate function be filled out in this particular case?
> 
> I'd like to defer to Biju, who added the empty round^Wdetermine rate function.

PLL is capable of generating any frequency. that is the reason.

But we could, call rzg2l_cpg_get_foutpostdiv_rate() from determine_rate()
as modified rzg2l_cpg_get_foutpostdiv_rate()[1] can return errors

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rzg2l-cpg.c?h=next-20260227#n590


Cheers,
Biju

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Brian Masney]

Hi Biju,

On Fri, Feb 27, 2026 at 03:23:19PM +0000, Biju Das wrote:
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 27 February 2026 15:09
> > Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use
> > CLK_ROUNDING_FW_MANAGED flag
> > 
> > On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> > > On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > > > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > > > This clk driver has a noop determine_rate clk op. Drop this empty
> > > > > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > > > >
> > > > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > 
> > > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > > >         init.name = core->name;
> > > > >         parent_name = __clk_get_name(parent);
> > > > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > > > -       init.flags = 0;
> > > > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> > > >
> > > > Iff this is the Right Thing To Do (TM), it needs a comment, as this
> > > > clock is not managed by firmware.
> > >
> > > Before I start a larger discussion on patch 1 with more people about a
> > > name for this flag, help me understand why this provider has a noop
> > > determine rate. Is the hardware eventually programmed with a rate
> > > that's close enough to what was passed in? Or it doesn't really matter
> > > what the clock rate is, just as long as it is running? Or should the
> > > determine_rate function be filled out in this particular case?
> > 
> > I'd like to defer to Biju, who added the empty round^Wdetermine rate function.
> 
> PLL is capable of generating any frequency. that is the reason.
> 
> But we could, call rzg2l_cpg_get_foutpostdiv_rate() from determine_rate()
> as modified rzg2l_cpg_get_foutpostdiv_rate()[1] can return errors
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rzg2l-cpg.c?h=next-20260227#n590

OK. So how do you all want to proceed here?

Do you want to fill out the determine rate in this driver? If so, we can
just drop this particular patch from this series.

Since the PLL is capable of any frequency, do you want to keep the empty
determine rate functionality? If so, we could use a different name for
this flag. Maybe CLK_ROUNDING_NOOP?

Brian

RE: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Biju Das]

Hi Brian,

> -----Original Message-----
> From: Brian Masney <bmasney@redhat.com>
> Sent: 27 February 2026 15:48
> Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use
> CLK_ROUNDING_FW_MANAGED flag
> 
> Hi Biju,
> 
> On Fri, Feb 27, 2026 at 03:23:19PM +0000, Biju Das wrote:
> > > -----Original Message-----
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: 27 February 2026 15:09
> > > Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop
> > > determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
> > >
> > > On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> > > > On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > > > > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > > > > This clk driver has a noop determine_rate clk op. Drop this
> > > > > > empty function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > > > > >
> > > > > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > >
> > > > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > > > >         init.name = core->name;
> > > > > >         parent_name = __clk_get_name(parent);
> > > > > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > > > > -       init.flags = 0;
> > > > > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> > > > >
> > > > > Iff this is the Right Thing To Do (TM), it needs a comment, as
> > > > > this clock is not managed by firmware.
> > > >
> > > > Before I start a larger discussion on patch 1 with more people
> > > > about a name for this flag, help me understand why this provider
> > > > has a noop determine rate. Is the hardware eventually programmed
> > > > with a rate that's close enough to what was passed in? Or it
> > > > doesn't really matter what the clock rate is, just as long as it
> > > > is running? Or should the determine_rate function be filled out in this particular case?
> > >
> > > I'd like to defer to Biju, who added the empty round^Wdetermine rate function.
> >
> > PLL is capable of generating any frequency. that is the reason.
> >
> > But we could, call rzg2l_cpg_get_foutpostdiv_rate() from
> > determine_rate() as modified rzg2l_cpg_get_foutpostdiv_rate()[1] can
> > return errors
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tr
> > ee/drivers/clk/renesas/rzg2l-cpg.c?h=next-20260227#n590
> 
> OK. So how do you all want to proceed here?
> 
> Do you want to fill out the determine rate in this driver? If so, we can just drop this particular
> patch from this series.

We plan to fill out the determine rate later, as it can return error.

> 
> Since the PLL is capable of any frequency, do you want to keep the empty determine rate functionality?
> If so, we could use a different name for this flag. Maybe CLK_ROUNDING_NOOP?

I guess, maybe we could use CLK_ROUNDING_NOOP, till we have proper .determine_rate() for this driver???

Cheers,
Biju

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Brian Masney]

On Fri, Feb 27, 2026 at 03:57:28PM +0000, Biju Das wrote:
> > -----Original Message-----
> > From: Brian Masney <bmasney@redhat.com>
> > Sent: 27 February 2026 15:48
> > Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use
> > CLK_ROUNDING_FW_MANAGED flag
> > 
> > Hi Biju,
> > 
> > On Fri, Feb 27, 2026 at 03:23:19PM +0000, Biju Das wrote:
> > > > -----Original Message-----
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > Sent: 27 February 2026 15:09
> > > > Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop
> > > > determine_rate op and use CLK_ROUNDING_FW_MANAGED flag
> > > >
> > > > On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> > > > > On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > > > > > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > > > > > This clk driver has a noop determine_rate clk op. Drop this
> > > > > > > empty function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > > > > > >
> > > > > > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > >
> > > > > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > > > > >         init.name = core->name;
> > > > > > >         parent_name = __clk_get_name(parent);
> > > > > > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > > > > > -       init.flags = 0;
> > > > > > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> > > > > >
> > > > > > Iff this is the Right Thing To Do (TM), it needs a comment, as
> > > > > > this clock is not managed by firmware.
> > > > >
> > > > > Before I start a larger discussion on patch 1 with more people
> > > > > about a name for this flag, help me understand why this provider
> > > > > has a noop determine rate. Is the hardware eventually programmed
> > > > > with a rate that's close enough to what was passed in? Or it
> > > > > doesn't really matter what the clock rate is, just as long as it
> > > > > is running? Or should the determine_rate function be filled out in this particular case?
> > > >
> > > > I'd like to defer to Biju, who added the empty round^Wdetermine rate function.
> > >
> > > PLL is capable of generating any frequency. that is the reason.
> > >
> > > But we could, call rzg2l_cpg_get_foutpostdiv_rate() from
> > > determine_rate() as modified rzg2l_cpg_get_foutpostdiv_rate()[1] can
> > > return errors
> > >
> > > [1]
> > > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tr
> > > ee/drivers/clk/renesas/rzg2l-cpg.c?h=next-20260227#n590
> > 
> > OK. So how do you all want to proceed here?
> > 
> > Do you want to fill out the determine rate in this driver? If so, we can just drop this particular
> > patch from this series.
> 
> We plan to fill out the determine rate later, as it can return error.

OK, if you are planning to fill out the determine rate, then I'll just
skip over this driver to avoid the code churn.

Brian

Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Geert Uytterhoeven]

Hi Biju,

On Fri, 27 Feb 2026 at 16:57, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Brian Masney <bmasney@redhat.com>
> > On Fri, Feb 27, 2026 at 03:23:19PM +0000, Biju Das wrote:
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> > > > > On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > > > > > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > > > > > This clk driver has a noop determine_rate clk op. Drop this
> > > > > > > empty function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > > > > > >
> > > > > > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > >
> > > > > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > > > > >         init.name = core->name;
> > > > > > >         parent_name = __clk_get_name(parent);
> > > > > > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > > > > > -       init.flags = 0;
> > > > > > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> > > > > >
> > > > > > Iff this is the Right Thing To Do (TM), it needs a comment, as
> > > > > > this clock is not managed by firmware.
> > > > >
> > > > > Before I start a larger discussion on patch 1 with more people
> > > > > about a name for this flag, help me understand why this provider
> > > > > has a noop determine rate. Is the hardware eventually programmed
> > > > > with a rate that's close enough to what was passed in? Or it
> > > > > doesn't really matter what the clock rate is, just as long as it
> > > > > is running? Or should the determine_rate function be filled out in this particular case?
> > > >
> > > > I'd like to defer to Biju, who added the empty round^Wdetermine rate function.
> > >
> > > PLL is capable of generating any frequency. that is the reason.
> > >
> > > But we could, call rzg2l_cpg_get_foutpostdiv_rate() from
> > > determine_rate() as modified rzg2l_cpg_get_foutpostdiv_rate()[1] can
> > > return errors
> > >
> > > [1]
> > > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tr
> > > ee/drivers/clk/renesas/rzg2l-cpg.c?h=next-20260227#n590
> >
> > OK. So how do you all want to proceed here?
> >
> > Do you want to fill out the determine rate in this driver? If so, we can just drop this particular
> > patch from this series.
>
> We plan to fill out the determine rate later, as it can return error.
>
> >
> > Since the PLL is capable of any frequency, do you want to keep the empty determine rate functionality?
> > If so, we could use a different name for this flag. Maybe CLK_ROUNDING_NOOP?
>
> I guess, maybe we could use CLK_ROUNDING_NOOP, till we have proper .determine_rate() for this driver???

Just keeping the empty function should work, too, right?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 27 February 2026 16:01
> 
> Hi Biju,
> 
> On Fri, 27 Feb 2026 at 16:57, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: Brian Masney <bmasney@redhat.com> On Fri, Feb 27, 2026 at
> > > 03:23:19PM +0000, Biju Das wrote:
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Fri, 27 Feb
> > > > > 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> > > > > > On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > > > > > > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > > > > > > This clk driver has a noop determine_rate clk op. Drop
> > > > > > > > this empty function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > > > > > > >
> > > > > > > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> > > > > > >
> > > > > > > Thanks for your patch!
> > > > > > >
> > > > > > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > > > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > > >
> > > > > > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > > > > > >         init.name = core->name;
> > > > > > > >         parent_name = __clk_get_name(parent);
> > > > > > > >         init.ops = &rzg2l_cpg_sipll5_ops;
> > > > > > > > -       init.flags = 0;
> > > > > > > > +       init.flags = CLK_ROUNDING_FW_MANAGED;
> > > > > > >
> > > > > > > Iff this is the Right Thing To Do (TM), it needs a comment,
> > > > > > > as this clock is not managed by firmware.
> > > > > >
> > > > > > Before I start a larger discussion on patch 1 with more people
> > > > > > about a name for this flag, help me understand why this
> > > > > > provider has a noop determine rate. Is the hardware eventually
> > > > > > programmed with a rate that's close enough to what was passed
> > > > > > in? Or it doesn't really matter what the clock rate is, just
> > > > > > as long as it is running? Or should the determine_rate function be filled out in this
> particular case?
> > > > >
> > > > > I'd like to defer to Biju, who added the empty round^Wdetermine rate function.
> > > >
> > > > PLL is capable of generating any frequency. that is the reason.
> > > >
> > > > But we could, call rzg2l_cpg_get_foutpostdiv_rate() from
> > > > determine_rate() as modified rzg2l_cpg_get_foutpostdiv_rate()[1]
> > > > can return errors
> > > >
> > > > [1]
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.gi
> > > > t/tr
> > > > ee/drivers/clk/renesas/rzg2l-cpg.c?h=next-20260227#n590
> > >
> > > OK. So how do you all want to proceed here?
> > >
> > > Do you want to fill out the determine rate in this driver? If so, we
> > > can just drop this particular patch from this series.
> >
> > We plan to fill out the determine rate later, as it can return error.
> >
> > >
> > > Since the PLL is capable of any frequency, do you want to keep the empty determine rate
> functionality?
> > > If so, we could use a different name for this flag. Maybe CLK_ROUNDING_NOOP?
> >
> > I guess, maybe we could use CLK_ROUNDING_NOOP, till we have proper .determine_rate() for this
> driver???
> 
> Just keeping the empty function should work, too, right?

Yes, it will work.

Cheers,
Biju

Re: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Brian Masney]

On Thu, Feb 26, 2026 at 01:16:45PM -0500, Brian Masney wrote:
> There are some clocks where the rounding is managed by the hardware, and
> the determine_rate() clk ops is just a noop that simply returns 0. Add a
> new flag for these type of clocks, and update the clk core so that the
> determine_rate() clk op is not required when this flag is set.
> 
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> 
...
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 1cda2c78dffaff037f0f16b0f11106b63b3a746f..187f8248a9c840c701cbbba99bb7cdeef7b654ee 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -32,6 +32,8 @@
>  #define CLK_OPS_PARENT_ENABLE	BIT(12)
>  /* duty cycle call may be forwarded to the parent clock */
>  #define CLK_DUTY_CYCLE_PARENT	BIT(13)
> +/* clock rate rounding is managed by firmware, don't require determine_rate */
> +#define CLK_ROUNDING_FW_MANAGED		BIT(14)

Based on a conversation in the Renesas driver change, I think we should
rename this flag to CLK_ROUNDING_NOOP. Let me know if there are any
objections, or suggestions for a better name. I'll let let this sit out
there for about a week or so before sending a v2.

Brian

Re: [PATCH 01/13] clk: add new flag CLK_ROUNDING_FW_MANAGED

[Sudeep Holla]

On Thu, Feb 26, 2026 at 01:16:45PM -0500, Brian Masney wrote:
> There are some clocks where the rounding is managed by the hardware, and
> the determine_rate() clk ops is just a noop that simply returns 0. Add a
> new flag for these type of clocks, and update the clk core so that the
> determine_rate() clk op is not required when this flag is set.
> 
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> 

Acked-by: Sudeep Holla <sudeep.holla@kernel.org>

-- 
Regards,
Sudeep