Re: [PATCH v3 3/3] drm: renesas: rzg2l_mipi_dsi: Fix deassert/assert of CMN_RSTB signal

Tommaso Merciai
2026-04-10T08:56:12Z

On Mon, Mar 30, 2026 at 11:44:46AM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The RZ/G2L hardware manual (Rev. 1.50, May 2025), Section 34.4.2.1,
> requires deasserting the CMN_RSTB signal after setting the Link registers.
> Move the reset_control_deassert() call from rzg2l_mipi_dsi_dphy_init() to
> rzg2l_mipi_dsi_startup(), placing it after the Link register writes. This
> reset signal is optional for RZ/V2H SoCs, so add a NULL check. Drop the
> unused ret variable from rzg2l_mipi_dsi_dphy_init().
>
> The CMN_RSTB signal is not required for reading PHY registers in the
> probe. Move reset_control_assert() from rzg2l_mipi_dsi_dphy_exit() to
> rzg2l_mipi_dsi_stop(), placing it before the dphy_exit() call. Since this
> reset signal is optional for RZ/V2H, the call is a no-op on that SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Looks good to me, thanks.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind Regards,
Tommaso

> ---
> v2->v3:
> * Merged patch#2 and patch#3 to avoid breakage.
> * Updated commit description
> v1->v2:
> * Updated commit header and description
> * Moved the code from rzg2l_mipi_dsi_dphy_init() to rzg2l_mipi_dsi_startup()
> * Moved the check before calling reset_control_deassert(), so that it will be
> skipped for RZ/V2H SoC
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 9d9f77d8f949..715872130780 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -484,7 +484,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> u32 dphytim1;
> u32 dphytim2;
> u32 dphytim3;
> - int ret;
>
> /* All DSI global operation timings are set with recommended setting */
> for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) {
> @@ -524,12 +523,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2);
> rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3);
>
> - ret = reset_control_deassert(dsi->rstc);
> - if (ret < 0)
> - return ret;
> -
> - fsleep(1000);
> -
> return 0;
> }
>
> @@ -541,8 +534,6 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
>
> dphyctrl0 &= ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR);
> rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
> -
> - reset_control_assert(dsi->rstc);
> }
>
> static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
> @@ -811,6 +802,14 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> FIELD_MODIFY(DSISETR_MRPSZ, &dsisetr, RZG2L_DCS_BUF_SIZE);
> rzg2l_mipi_dsi_link_write(dsi, DSISETR, dsisetr);
>
> + if (dsi->rstc) {
> + ret = reset_control_deassert(dsi->rstc);
> + if (ret < 0)
> + goto err_phy;
> +
> + fsleep(1000);
> + }
> +
> return 0;
>
> err_phy:
> @@ -822,6 +821,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
>
> static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)
> {
> + reset_control_assert(dsi->rstc);
> dsi->info->dphy_exit(dsi);
> pm_runtime_put(dsi->dev);
> }
> --
> 2.43.0
>