Linux Renesas SOC kernel development
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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Biju <biju.das.au@gmail.com>
Cc: Ulf Hansson <ulfh@kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v24 07/15] mmc: renesas_sdhi: Add tuning delay support for RZ/G2L
Date: Thu, 3 Sep 2026 11:30:20 +0200	[thread overview]
Message-ID: <apk-J8is9MNm7I2R@shikoro> (raw)
In-Reply-To: <20260820171657.62815-8-biju.das.jz@bp.renesas.com>

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> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] The new function renesas_sdhi_set_hw_adjustment_delay() accesses SCC registers via sd_scc_write32() without checking if priv->scc_ctl is initialized.
> --
> 
> --- Patch [7]: [PATCH v24 07/15] mmc: renesas_sdhi: Add tuning delay support for RZ/G2L ---
> commit 4e31e96fb980d0bb6400d3a60dfcc29dca208dcc
> Author: Biju Das <biju.das.jz@bp.renesas.com>
> 
> mmc: renesas_sdhi: Add tuning delay support for RZ/G2L
> 
> This commit adds hardware adjustment delay support for RZ/G2L SoCs during
> signal-voltage switch. It introduces the TMIO_MMC_TUNING_DELAY flag and
> applies a delay by writing to SCC_TMPPORT2 based on the regulator voltage.
> 
> > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
> > --- a/drivers/mmc/host/renesas_sdhi_core.c
> > +++ b/drivers/mmc/host/renesas_sdhi_core.c
> [ ... ]
> > @@ -350,6 +316,55 @@ static inline void sd_scc_write32(struct tmio_mmc_host *host,
> >  	writel(val, priv->scc_ctl + (addr << host->bus_shift));
> >  }
> >  
> > +static void renesas_sdhi_set_hw_adjustment_delay(struct tmio_mmc_host *host)
> > +{
> > +	struct renesas_sdhi *priv = host_to_priv(host);
> > +
> > +	if (!(host->pdata->flags & TMIO_MMC_TUNING_DELAY))
> > +		return;
> > +
> > +	if (host->mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
> > +		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x0);
> > +	else
> > +		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x1);
> 
> [Severity: High]
> Is it possible for priv->scc_ctl to be NULL here?
> 
> If an incorrect device tree binding or a hardware fault causes the
> controller to report a version older than SDHI_VER_GEN2_SDR104,
> priv->scc_ctl might not be mapped during probe.
> 
> However, renesas_sdhi_start_signal_voltage_switch() is registered based
> on TMIO_MMC_MIN_RCAR2 and calls this new function, which writes directly
> to the SCC register via sd_scc_write32().
> 
> Could this cause a NULL pointer dereference during card insertion?

I agree. We should ensure in probe() that either

a) TMIO_MMC_TUNING_DELAY has a valid SCC or bail out otherwise

or

b) clear the TMIO_MMC_TUNING_DELAY flag if there is no SCC present

What do you think?


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  reply	other threads:[~2026-09-03  9:30 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-20 17:16 [PATCH v24 00/15] Add Renesas RZ/G3L SD/eMMC support Biju
2026-08-20 17:16 ` [PATCH v24 01/15] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju
2026-09-02 10:45   ` Wolfram Sang
2026-08-20 17:16 ` [PATCH v24 02/15] mmc: renesas_sdhi: Clean up whitespace and add OF table sentinels Biju
2026-09-02 10:47   ` Wolfram Sang
2026-09-04  6:40     ` Biju Das
2026-08-20 17:16 ` [PATCH v24 03/15] mmc: renesas_sdhi: Add clk_mask field to support flexible clock divider widths Biju
2026-09-02 10:51   ` Wolfram Sang
2026-09-04 10:54     ` Biju Das
2026-09-02 10:54   ` Wolfram Sang
2026-09-04 11:03     ` Biju Das
2026-08-20 17:16 ` [PATCH v24 04/15] mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock ranges Biju
2026-09-02 11:05   ` Wolfram Sang
2026-09-04 12:46     ` Biju Das
2026-08-20 17:16 ` [PATCH v24 05/15] mmc: renesas_sdhi: Add SDHI_SD_CLK_CTL_DIV1 macro for 1/1 option Biju
2026-09-02 11:06   ` Wolfram Sang
2026-08-20 17:16 ` [PATCH v24 06/15] mmc: renesas_sdhi: Make clock divider mask configurable Biju
2026-09-02 11:09   ` Wolfram Sang
2026-09-04 12:48     ` Biju Das
2026-08-20 17:16 ` [PATCH v24 07/15] mmc: renesas_sdhi: Add tuning delay support for RZ/G2L Biju
2026-09-03  9:30   ` Wolfram Sang [this message]
2026-09-04 14:47     ` Biju Das
2026-09-03  9:34   ` Wolfram Sang
2026-09-04 15:15     ` Biju Das
2026-08-20 17:16 ` [PATCH v24 08/15] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag Biju
2026-09-03  9:37   ` Wolfram Sang
2026-09-03  9:43   ` Wolfram Sang
2026-08-20 17:16 ` [PATCH v24 09/15] mmc: renesas_sdhi: Add optional axis/axim reset controls Biju
2026-09-03  9:48   ` Wolfram Sang
2026-08-20 17:16 ` [PATCH v24 10/15] mmc: renesas_sdhi: Add write32_hook for CTL_SD_CARD_CLK_CTL register writes Biju
2026-09-03 10:30   ` Wolfram Sang
2026-09-03 10:32   ` Wolfram Sang
2026-08-20 17:16 ` [PATCH v24 11/15] mmc: renesas_sdhi: Add RZ/G3L SDHI support Biju
2026-09-03 12:01   ` Wolfram Sang
2026-08-20 17:16 ` [PATCH v24 12/15] mmc: renesas_sdhi: Save and restore IOVS across suspend/resume Biju
2026-08-20 17:16 ` [PATCH v24 13/15] mmc: renesas_sdhi: Make HS400 OSEL bit configurable per SoC Biju
2026-08-20 17:16 ` [PATCH v24 14/15] mmc: renesas_sdhi: Add RZ/G3L HS400 support Biju
2026-08-20 17:16 ` [PATCH v24 15/15] mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L Biju
2026-09-01 14:52 ` [PATCH v24 00/15] Add Renesas RZ/G3L SD/eMMC support Wolfram Sang
2026-09-03 20:11 ` Wolfram Sang
2026-09-04  2:24   ` Biju Das
2026-09-04  8:00   ` Geert Uytterhoeven

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