[GIT PULL] clk: renesas: Updates for v5.16

[Geert Uytterhoeven <geert+renesas@glider.be>]

	Hi Mike, Stephen,

The following changes since commit fa2a30f8e0aa9304919750b116a9e9e322465299:

  clk: renesas: rzg2l: Fix clk status function (2021-09-24 15:11:05 +0200)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v5.16-tag1

for you to fetch changes up to cc3e8f97bbd370b51b3bb7fec391d65d461d7d02:

  clk: renesas: r8a779a0: Add Z0 and Z1 clock support (2021-09-28 09:28:53 +0200)

----------------------------------------------------------------
clk: renesas: Updates for v5.16

  - Add TPU (PWM), and Z (Cortex-A76) clocks on R-Car V3U,
  - Add Ethernet clocks on RZ/G2L.

Thanks for pulling!
----------------------------------------------------------------
Biju Das (4):
      clk: renesas: rzg2l: Add support to handle MUX clocks
      clk: renesas: r9a07g044: Add ethernet clock sources
      clk: renesas: rzg2l: Add support to handle coupled clocks
      clk: renesas: r9a07g044: Add GbEthernet clock/reset

Geert Uytterhoeven (1):
      clk: renesas: r8a779a0: Add Z0 and Z1 clock support

Wolfram Sang (1):
      clk: renesas: r8a779a0: Add TPU clock

 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 159 ++++++++++++++++++++++++++++++++
 drivers/clk/renesas/r9a07g044-cpg.c     |  29 +++++-
 drivers/clk/renesas/rzg2l-cpg.c         |  94 +++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h         |  26 +++++-
 4 files changed, 306 insertions(+), 2 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds