From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79D5ECCA47E for ; Wed, 8 Jun 2022 15:40:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244503AbiFHPkd (ORCPT ); Wed, 8 Jun 2022 11:40:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244478AbiFHPkb (ORCPT ); Wed, 8 Jun 2022 11:40:31 -0400 Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F7C01CC5FB for ; Wed, 8 Jun 2022 08:40:27 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:243a:e14b:d107:1f56]) by andre.telenet-ops.be with bizsmtp id gfgR270061qF9lr01fgRkM; Wed, 08 Jun 2022 17:40:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nyxnE-003E0A-PR; Wed, 08 Jun 2022 17:40:24 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nyxnE-008kJP-4K; Wed, 08 Jun 2022 17:40:24 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 0/4] arm64: dts: renesas: r8a779f0: CPU topology improvements Date: Wed, 8 Jun 2022 17:40:18 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi all, Currently, the R-Car S4-8 DTS describes a single Cortex-A55 CPU core only. This patch series completes the description of the Cortex-A55 lusters by describing L3 caches, CPU cores 1-7, CPU map, PSCI for CPU bring up, CPUIdle, and CPU core clocks. This has been tested on the Spider development board, where now all 8 Cortex-A55 CPU cores are available after boot. All but the first CPU core can be controlled from sysfs (/sys/*/*/cpu/cpu[0-7]/online). CPU core performance follows the CPU core clocks, when changing the frequency of the latter. I plan to queue this in renesas-devel for v5.20. Thanks for your comments! Geert Uytterhoeven (3): arm64: dts: renesas: r8a779f0: Add L3 cache controller arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores arm64: dts: renesas: r8a779f0: Add CPU core clocks Tho Vu (1): arm64: dts: renesas: r8a779f0: Add CPUIdle support arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 175 +++++++++++++++++++++- 1 file changed, 170 insertions(+), 5 deletions(-) -- 2.25.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds