From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks
Date: Fri, 7 Oct 2022 15:09:59 +0200 [thread overview]
Message-ID: <cover.1665147497.git.geert+renesas@glider.be> (raw)
Hi Mike, Stephen,
This patch series adds the various SASYNCPER clocks (used by modules
that must not be affected by Spread Spectrum and/or Fractional
Multiplication), and most of its derived module clocks (serial and PWM)
on the R-Car V4H (R8A7799G0) SoC.
As the second patch is a fix, and the first patch is a dependency (also
for a related DT fix), I plan to queue the first two patches in
renesas-clk-fixes for v6.1.
I plan to queue the last three patches in renesas-clk for v6.2.
Thanks for your comments!
Geert Uytterhoeven (5):
clk: renesas: r8a779g0: Add SASYNCPER clocks
clk: renesas: r8a779g0: Fix HSCIF parent clocks
clk: renesas: r8a779g0: Add SCIF clocks
clk: renesas: r8a779g0: Add PWM clock
clk: renesas: r8a779g0: Add TPU clock
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next reply other threads:[~2022-10-07 13:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-07 13:09 Geert Uytterhoeven [this message]
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
2022-10-09 21:20 ` Wolfram Sang
2022-10-10 11:15 ` Geert Uytterhoeven
2022-10-10 18:34 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 20:47 ` [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Stephen Boyd
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