[GIT PULL] clk: renesas: Updates for v6.14 (take two)

[Geert Uytterhoeven <geert+renesas@glider.be>]

	Hi Mike, Stephen,

The following changes since commit f962745289958e89bf520407728e384e52ea8e27:

  clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP (2024-12-10 12:02:24 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.14-tag2

for you to fetch changes up to e91609f1c3b0ce06d80b1b3bd0e6b942782be016:

  dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard (2025-01-07 17:03:01 +0100)

----------------------------------------------------------------
clk: renesas: Updates for v6.14 (take two)

  - Add support for the RZ/G3E (R9A09G047) SoC,
  - Add Module Stop (MSTOP) support on RZ/V2H,
  - Add Image Signal Processor helper block (FCPVX and VSPX) clocks on
    R-Car V4H SoC,
  - Add System Controller (SYS) reset and Generic Interrupt Controller
    (GIC) clock and reset entries on RZ/V2H,
  - Miscellaneous fixes and improvements.

Note that this includes DT binding and binding definitions for the
RZ/G3E SoC, which are shared by DT source files and drivers.

Thanks for pulling!

----------------------------------------------------------------
Biju Das (7):
      dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
      dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
      dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
      clk: renesas: rzv2h: Add MSTOP support
      clk: renesas: rzv2h: Add support for RZ/G3E SoC
      clk: renesas: r9a09g047: Add CA55 core clocks
      clk: renesas: r9a09g047: Add I2C clocks/resets

Geert Uytterhoeven (2):
      Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-clk-for-v6.14
      dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard

Jacopo Mondi (2):
      clk: renesas: r8a779g0: Add FCPVX clocks
      clk: renesas: r8a779g0: Add VSPX clocks

Lad Prabhakar (2):
      clk: renesas: r9a09g057: Add reset entry for SYS
      clk: renesas: r9a09g057: Add clock and reset entries for GIC

 .../bindings/clock/renesas,rzv2h-cpg.yaml          |  15 +-
 .../devicetree/bindings/soc/renesas/renesas.yaml   |  17 +++
 drivers/clk/renesas/Kconfig                        |   7 +-
 drivers/clk/renesas/Makefile                       |   1 +
 drivers/clk/renesas/r8a779g0-cpg-mssr.c            |   4 +
 drivers/clk/renesas/r9a09g047-cpg.c                | 150 +++++++++++++++++++
 drivers/clk/renesas/r9a09g057-cpg.c                | 160 ++++++++++++++-------
 drivers/clk/renesas/rzv2h-cpg.c                    | 152 +++++++++++++++++---
 drivers/clk/renesas/rzv2h-cpg.h                    |  31 +++-
 .../dt-bindings/clock/renesas,r9a08g045-vbattb.h   |   6 +-
 include/dt-bindings/clock/renesas,r9a09g047-cpg.h  |  21 +++
 11 files changed, 475 insertions(+), 89 deletions(-)
 create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds