From: Marek Vasut <marek.vasut@mailbox.org>
To: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>,
dri-devel@lists.freedesktop.org
Cc: stable@vger.kernel.org, David Airlie <airlied@gmail.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Magnus Damm <magnus.damm@gmail.com>,
Maxime Ripard <mripard@kernel.org>,
Simona Vetter <simona@ffwll.ch>,
Thomas Zimmermann <tzimmermann@suse.de>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v2] drm/rcar-du: dsi: Fix 1/2/3 lane support
Date: Sun, 31 Aug 2025 19:01:09 +0200 [thread overview]
Message-ID: <fa0d9882-aadd-49e4-8a39-e0d0c321ecc1@mailbox.org> (raw)
In-Reply-To: <d1354951-cbd3-4216-970b-e1e130f58522@ideasonboard.com>
On 8/14/25 7:54 AM, Tomi Valkeinen wrote:
Hello Tomi,
> On 14/08/2025 00:08, Marek Vasut wrote:
>> Remove fixed PPI lane count setup. The R-Car DSI host is capable
>> of operating in 1..4 DSI lane mode. Remove the hard-coded 4-lane
>> configuration from PPI register settings and instead configure
>> the PPI lane count according to lane count information already
>> obtained by this driver instance.
>>
>> Configure TXSETR register to match PPI lane count. The R-Car V4H
>> Reference Manual R19UH0186EJ0121 Rev.1.21 section 67.2.2.3 Tx Set
>> Register (TXSETR), field LANECNT description indicates that the
>> TXSETR register LANECNT bitfield lane count must be configured
>> such, that it matches lane count configuration in PPISETR register
>> DLEN bitfield. Make sure the LANECNT and DLEN bitfields are
>> configured to match.
>>
>> Fixes: 155358310f01 ("drm: rcar-du: Add R-Car DSI driver")
>> Cc: <stable@vger.kernel.org>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
>> ---
>> Cc: David Airlie <airlied@gmail.com>
>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>> Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Cc: Magnus Damm <magnus.damm@gmail.com>
>> Cc: Maxime Ripard <mripard@kernel.org>
>> Cc: Simona Vetter <simona@ffwll.ch>
>> Cc: Thomas Zimmermann <tzimmermann@suse.de>
>> Cc: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
>> Cc: dri-devel@lists.freedesktop.org
>> Cc: linux-renesas-soc@vger.kernel.org
>> ---
>> V2: - Split this out of a series, update commit message, combine from
>> drm/rcar-du: dsi: Remove fixed PPI lane count setup
>> drm/rcar-du: dsi: Configure TXSETR register to match PPI lane count
>> - add Fixes tag, CC stable
>> ---
>> drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 5 ++++-
>> drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 8 ++++----
>> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Would you like to pick this up via drm-misc , or shall I ?
next prev parent reply other threads:[~2025-08-31 17:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-13 21:08 [PATCH v2] drm/rcar-du: dsi: Fix 1/2/3 lane support Marek Vasut
2025-08-14 5:54 ` Tomi Valkeinen
2025-08-31 17:01 ` Marek Vasut [this message]
2025-09-01 9:22 ` Tomi Valkeinen
2025-09-01 10:13 ` Marek Vasut
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