Re: [PATCH RFC v3 05/11] RISC-V: QoS: add resctrl arch callbacks for CBQRI controllers

From: Reinette Chatre <reinette.chatre@intel.com>
To: "Drew Fustini" <fustini@kernel.org>,
	"Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Radim Krčmář" <rkrcmar@ventanamicro.com>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Adrien Ricciardi" <aricciardi@baylibre.com>,
	"Nicolas Pitre" <npitre@baylibre.com>,
	"Kornel Dulęba" <mindal@semihalf.com>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Vasudevan Srinivasan" <vasu@rivosinc.com>,
	"Ved Shanbhogue" <ved@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"yunhui cui" <cuiyunhui@bytedance.com>,
	"Chen Pei" <cp0613@linux.alibaba.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	guo.wenjia23@zte.com.cn,
	"Gong Shuai" <gong.shuai@sanechips.com.cn>,
	"Gong Shuai" <gsh517@gmail.com>,
	liu.qingtao2@zte.com.cn, "Tony Luck" <tony.luck@intel.com>,
	"Babu Moger" <babu.moger@amd.com>,
	"Peter Newman" <peternewman@google.com>,
	"Fenghua Yu" <fenghua.yu@intel.com>,
	"James Morse" <james.morse@arm.com>,
	"Ben Horgan" <ben.horgan@arm.com>,
	"Dave Martin" <Dave.Martin@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>,
	"Robert Moore" <robert.moore@intel.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<x86@kernel.org>, <linux-acpi@vger.kernel.org>,
	<acpica-devel@lists.linux.dev>, <devicetree@vger.kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH RFC v3 05/11] RISC-V: QoS: add resctrl arch callbacks for CBQRI controllers
Date: Thu, 30 Apr 2026 16:17:22 -0700	[thread overview]
Message-ID: <03085c36-315a-47c8-85aa-f3de88fa43bd@intel.com> (raw)
In-Reply-To: <20260414-ssqosid-cbqri-rqsc-v7-0-v3-5-b3b2e7e9847a@kernel.org>

Hi Drew,

On 4/14/26 6:53 PM, Drew Fustini wrote:

> +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d,
> +			    u32 closid, enum resctrl_conf_type t, u32 cfg_val)
> +{
> +	struct cbqri_controller *ctrl;
> +	struct cbqri_resctrl_dom *dom;
> +	struct cbqri_config cfg;
> +	int err = 0;
> +
> +	dom = container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom);
> +	ctrl = dom->hw_ctrl;
> +
> +	if (!r->alloc_capable)
> +		return -EINVAL;
> +
> +	switch (r->rid) {
> +	case RDT_RESOURCE_L2:
> +	case RDT_RESOURCE_L3:
> +		cfg.cbm = cfg_val;
> +		err = cbqri_apply_cache_config(dom, closid, t, &cfg);
> +		break;
> +	case RDT_RESOURCE_MBA:
> +		/* convert from percentage to bandwidth blocks */
> +		cfg.rbwb = cfg_val * ctrl->bc.nbwblks / 100;
> +		cfg.rbwb = min_t(u64, cfg.rbwb, ctrl->bc.mrbwb);
> +		err = cbqri_apply_bw_config(dom, closid, t, &cfg);

(Earlier comment wondered about whether rbwb cannot just be provided
directly to cbqri_apply_bw_config().)

Apart from that it looks like this can benefit from "emulated controls"
that we mused about at https://lore.kernel.org/lkml/e788ca62-ec63-4552-978b-9569f369afd5@intel.com/

At this time this MBA resource is constrained by the 1% steps that the
default MB control supports and clearly it is emulated with a control that
can support finer granularities. I am currently working on a PoC of the
base schema descriptions on which the support for emulated controls can
be built that should be able to expose full hardware capability.

Reinette

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