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Wed, 12 Jul 2023 05:30:08 -0700 (PDT) Received: from [192.168.1.20] ([178.197.223.104]) by smtp.gmail.com with ESMTPSA id s17-20020a056402165100b0051dd19d6d6esm2732667edx.73.2023.07.12.05.30.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Jul 2023 05:30:08 -0700 (PDT) Message-ID: <0865b422-d587-c1c7-9463-510832ddddf4@linaro.org> Date: Wed, 12 Jul 2023 14:30:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin Cc: conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dslin1010@gmail.com, Zong Li , vincent.chen@sifive.com, Greentime Hu , Palmer Dabbelt , Paul Walmsley References: <20230616063210.19063-1-eric.lin@sifive.com> <20230616063210.19063-4-eric.lin@sifive.com> <2437bda9-bbdb-ad80-7201-1e16e1388890@linaro.org> <8c9ed2d4-83ab-ecc0-a300-e6bc8e2047b6@linaro.org> <20230712110908.GA23216@hsinchu16> From: Krzysztof Kozlowski In-Reply-To: <20230712110908.GA23216@hsinchu16> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230712_053010_904955_3CF6F5C2 X-CRM114-Status: GOOD ( 19.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 12/07/2023 13:09, Eric Lin wrote: > On Sat, Jul 01, 2023 at 10:22:25AM +0200, Krzysztof Kozlowski wrote: >> On 28/06/2023 18:31, Eric Lin wrote: >> >>>>>> >>>>>>> + - enum: >>>>>>> + - sifive,pL2Cache0 >>>>>>> + - sifive,pL2Cache1 >>>>>> >>>>>> What is "0" and "1" here? What do these compatibles represent? Why they >>>>>> do not have any SoC related part? >>>>> >>>>> The pL2Cache1 has minor changes in hardware, but it can use the same >>>>> pl2 cache driver. >>>> >>>> Then why aren't they compatible? >>>> >>> >>> The pL2Cache1 has removed some unused bits in the register compared to >>> pl2Cache0. >>> From the hardware perspective, they are not compatible but they can >>> share the same pl2 cache driver in software. >> >> So they are compatible... If they were not compatible, you wouldn't be >> able to use the same match in the driver. >> >>> Thus, we would like to keep both. It would be great if you can provide >>> some suggestions. Thanks. >> >> I propose to make them compatible, like every other piece of SoC. I >> don't see any benefit of having them separate. >> > > Hi Krzysztof, > > Sorry for the late reply. > The pl2 cache is our internal platform IP and is not part of any SoC. > > The reason why this driver is compatible with the hardware "pl2cache0" and hardware "pl2cache1" > is that it doesn't program the different parts of the config register > However, our internal software (e.g., bare-metal software) will program these different parts, > so it needs to rely on the different compatible string to identify the hardware. > > Additionally, we would like the compatible strings to reflect which hardware is being used Thanks. I don't understand how does it contradicts anything I said. So you do agree with me? Or what? Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv