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Thu, 30 Nov 2023 14:04:51 +0800 From: JeeHeng Sia To: Conor Dooley CC: "kernel@esmil.dk" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "krzk@kernel.org" , "conor+dt@kernel.org" , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "daniel.lezcano@linaro.org" , "tglx@linutronix.de" , "anup@brainfault.org" , "gregkh@linuxfoundation.org" , "jirislaby@kernel.org" , "michal.simek@amd.com" , Michael Zhu , "drew@beagleboard.org" , "devicetree@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Leyfoon Tan Subject: RE: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Thread-Topic: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Thread-Index: AQHaIol1JcCnwq8cUEOHXow7o5B+9LCQ2lcAgAGGuzA= Date: Thu, 30 Nov 2023 06:04:51 +0000 Message-ID: <08daada77b3e40049ef83f4eb762240c@EXMBX066.cuchost.com> References: <20231129060043.368874-1-jeeheng.sia@starfivetech.com> <20231129060043.368874-2-jeeheng.sia@starfivetech.com> <20231129-revisit-prefix-5327168e91f3@spud> In-Reply-To: <20231129-revisit-prefix-5327168e91f3@spud> Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [202.188.176.82] x-yovoleruleagent: yovoleflag MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231129_220541_745165_EE809355 X-CRM114-Status: GOOD ( 15.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Conor Dooley > Sent: Wednesday, November 29, 2023 10:46 PM > To: JeeHeng Sia > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > ; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Leyfoon Tan > Subject: Re: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles > > On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote: > > Add new compatible strings for Dubhe-80 and Dubhe-90. These are > > RISC-V cpu core from StarFive Technology and are used in StarFive > > JH8100 SoC. > > > > Signed-off-by: Sia Jee Heng > > Reviewed-by: Ley Foon Tan > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..493972b29a22 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -48,6 +48,8 @@ properties: > > - thead,c906 > > - thead,c910 > > - thead,c920 > > + - starfive,dubhe-80 > > + - starfive,dubhe-90 > > s goes before t. Noted. Will fix it. > > Cheers, > Conor. > > > - const: riscv > > - items: > > - enum: > > -- > > 2.34.1 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv