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From: Troy Mitchell <troy.mitchell@linux.spacemit.com>
To: Junhui Liu <junhui.liu@pigmoral.tech>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	Troy Mitchell <troy.mitchell@linux.spacemit.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC
Date: Mon, 27 Oct 2025 09:22:14 +0800	[thread overview]
Message-ID: <0E60AA15166FED21+aP7JRmPzDIq2WhWw@kernel.org> (raw)
In-Reply-To: <20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech>

On Sun, Oct 26, 2025 at 10:00:40PM +0800, Junhui Liu wrote:
> This adds Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC,
> as well as corresponding dts bindings and dts integration.
> 
> The CRU driver framework is built around the clock controller as the
> primary device, with the reset controller implemented as an auxiliary
> device. The clock part refers to the vendor's code [1] to determine the
> structure of the clock tree.
> 
> The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei
> UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64
> core). Most of the clock tree and CRU design can be shared between them.
> This series only adds CRU support for DR1V90. Nevertheless, the driver
> is structured to make future extension to other DR1 variants like
> DR1M90.
> 
> This depends on the basic dt series for DR1V90 SoC [2].
> 
> Link: https://gitee.com/anlogic/linux/blob/anlogic-6.1.54/drivers/clk/anlogic/anl_dr1x90_crp.c [1]
> Link: https://lore.kernel.org/all/20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech/ [2]
> ---
Do we really need a cover-letter? Since you only have one patch, Is it
better to put the above information below the --- line in the actual patch?

                                      - Troy

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  parent reply	other threads:[~2025-10-27  1:23 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-26 14:00 [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
2025-10-26 14:00 ` [PATCH v2 1/6] clk: correct clk_div_mask() return value for width == 32 Junhui Liu
2025-10-26 14:00 ` [PATCH v2 2/6] dt-bindings: clock: add Anlogic DR1V90 CRU Junhui Liu
2025-10-26 14:00 ` [PATCH v2 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC Junhui Liu
2025-10-26 14:00 ` [PATCH v2 4/6] reset: anlogic: add support for Anlogic DR1V90 resets Junhui Liu
2025-10-28  8:17   ` Philipp Zabel
2025-10-28 11:29     ` Junhui Liu
2025-10-26 14:00 ` [PATCH v2 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 Junhui Liu
2025-10-26 14:00 ` [PATCH v2 6/6] MAINTAINERS: Add entry for Anlogic DR1V90 SoC drivers Junhui Liu
2025-10-27  1:22 ` Troy Mitchell [this message]
2025-10-27  1:39   ` [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
2025-10-27  1:46     ` Troy Mitchell

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