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From: <Conor.Dooley@microchip.com>
To: <zongbox@gmail.com>
Cc: <ben.dooks@codethink.co.uk>, <ben.dooks@sifive.com>,
	<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
	<aou@eecs.berkeley.edu>, <greentime.hu@sifive.com>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache
Date: Wed, 31 Aug 2022 06:25:48 +0000	[thread overview]
Message-ID: <0deb3350-5a4a-8850-7dc1-e7e5b7e9bfdd@microchip.com> (raw)
In-Reply-To: <CA+ZOyah1Dwf1L9Mn50+v5tLToyktmmASeA5CutW5uwNybDG_Ow@mail.gmail.com>

On 31/08/2022 06:17, Zong Li wrote:
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> 
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> 
> <Conor.Dooley@microchip.com> 於 2022年8月31日 週三 凌晨1:09寫道:
>> That would keep the enforcement for existing caches and allow you
>> the freedome to do w/e you want for the ccache0 compatible.
> 
> Thanks you all for bring me here,  we actually have some core series
> with 4096 cache set in ccache, should we need to extend the cache set
> as follow? or we only need to focus on the DTS which is already in
> mainline.
> 
> cache-sets:
> -    enum: [1024, 2048]
> +   enum: [1024, 2048, 4096]

Until a user shows up, I think we are better off not adding 4096.

>>> Do we need someone to take charge of this series?
>>>
>>
>> Can I volunteer Zong? (since all but two of the patches are theirs)
>>
> 
> It is ok to me, but I'm still refining the patchset for V2, and I'm
> not sure if we will need the V3. Do you prefer to take V2 patch set
> first and replace the dt-binding patch?

If you could incorporate it for v2 it would make reviewing easier
I think.

Thanks,
Conor.
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  reply	other threads:[~2022-08-31  6:26 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-29  6:21 [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE Zong Li
2022-08-29  6:22 ` [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache Zong Li
2022-08-29  6:45   ` Conor.Dooley
2022-08-29  7:38     ` Zong Li
2022-08-29 18:42   ` Rob Herring
2022-08-30  2:57     ` Zong Li
2022-10-07  2:58   ` Palmer Dabbelt
2022-10-07  3:51     ` Zong Li
2022-08-29  6:22 ` [PATCH 2/3] soc: sifive: l2 cache: Rename " Zong Li
2022-08-29  7:05   ` Conor.Dooley
2022-08-29  8:40     ` Zong Li
2022-08-30  8:41       ` Conor.Dooley
2022-08-31  5:31         ` Zong Li
2022-08-30  8:18   ` Ben Dooks
2022-08-29  6:22 ` [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
2022-10-07  2:58   ` Palmer Dabbelt
2022-08-30  7:59 ` [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE Ben Dooks
2022-08-31  8:23   ` Zong Li
2022-08-30  8:26 ` [PATCH] soc: sifive: ccache: reduce printing on init Ben Dooks
2022-08-30 16:30   ` Conor.Dooley
2022-08-30 17:03     ` Ben Dooks
2022-08-31  5:22       ` Zong Li
2022-08-31 15:55         ` Ben Dooks
2022-09-01  8:34           ` Zong Li
2022-08-30  8:36 ` [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache Ben Dooks
2022-08-30 12:47   ` Rob Herring
2022-08-30 12:51 ` [RESEND PATCH] " Ben Dooks
2022-08-30 12:56   ` Conor.Dooley
2022-08-30 12:58     ` Ben Dooks
2022-08-30 13:49       ` Conor.Dooley
2022-08-30 16:49         ` Ben Dooks
2022-08-30 17:08           ` Conor.Dooley
2022-08-31  5:17             ` Zong Li
2022-08-31  6:25               ` Conor.Dooley [this message]
2022-09-02 19:36   ` Rob Herring

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