From: Yanteng Si <si.yanteng@linux.dev>
To: Han Gao <rabenda.cn@gmail.com>, linux-riscv@lists.infradead.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Charlie Jenkins <charlie@rivosinc.com>,
Andy Chiu <andybnac@gmail.com>, Jesse Taube <jesse@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] riscv: vector: Fix context save/restore with xtheadvector
Date: Mon, 26 May 2025 10:37:25 +0800 [thread overview]
Message-ID: <0f20ac8a-317c-4ce9-8c17-113f7eb6ad90@linux.dev> (raw)
In-Reply-To: <9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com>
在 5/23/25 6:25 PM, Han Gao 写道:
> Previously only v0-v7 were correctly saved/restored,
> and the context of v8-v31 are damanged.
> Correctly save/restore v8-v31 to avoid breaking userspace.
>
> Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Yanteng Si <si.yanteng@linux.dev>
Thanks,
Yanteng
> ---
>
> Changes in v2:
> Add fix tag
> Improve commit mesage
>
> v1: https://lore.kernel.org/linux-riscv/c221c98dc2369ea691e3eb664bf084dc909496f6.1747934680.git.rabenda.cn@gmail.com/
>
> arch/riscv/include/asm/vector.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index e8a83f55be2b..7df6355023a3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
> THEAD_VSETVLI_T4X0E8M8D1
> THEAD_VSB_V_V0T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V8T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V16T0
> "add t0, t0, t4\n\t"
> - THEAD_VSB_V_V0T0
> + THEAD_VSB_V_V24T0
> : : "r" (datap) : "memory", "t0", "t4");
> } else {
> asm volatile (
> @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
> THEAD_VSETVLI_T4X0E8M8D1
> THEAD_VLB_V_V0T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V8T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V16T0
> "add t0, t0, t4\n\t"
> - THEAD_VLB_V_V0T0
> + THEAD_VLB_V_V24T0
> : : "r" (datap) : "memory", "t0", "t4");
> } else {
> asm volatile (
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next prev parent reply other threads:[~2025-05-26 2:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-23 10:25 [PATCH v2] riscv: vector: Fix context save/restore with xtheadvector Han Gao
2025-05-24 9:58 ` Andy Chiu
2025-05-26 2:37 ` Yanteng Si [this message]
2025-06-12 20:10 ` patchwork-bot+linux-riscv
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