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Fri, 11 Sep 2026 01:43:31 -0700 (PDT) Received: from [192.168.0.13] ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc4c657156bsm813945a12.21.2026.09.11.01.43.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Sep 2026 01:43:30 -0700 (PDT) Message-ID: <0f82c603-0ddd-4d01-bf48-56d0ffcd29b0@gmail.com> Date: Fri, 11 Sep 2026 01:43:15 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/6] spacemit: k3: Replace bad CLINT node with ACLINT nodes To: Junhui Liu , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Inochi Amaoto , Radu Rendec , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Anup Patel , Guodong Xu , Albert Ou , Alexandre Ghiti Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Conor Dooley References: <20260909-k3-aclint-v2-0-7931e5bc86ad@pigmoral.tech> Content-Language: en-US From: Bo Gan In-Reply-To: <20260909-k3-aclint-v2-0-7931e5bc86ad@pigmoral.tech> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260911_014332_624744_AA853A2B X-CRM114-Status: GOOD ( 20.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Junhui, Thanks for your patch. This would give me more clarity while reviewing the OpenSBI patchset from Troy, and I was wondering why Troy sent this https://lore.kernel.org/opensbi/20260908-ipi-clear-all-v1-1-b1bd5d016eb6@linux.dev/T/#u Now it's much clearer -- K3 has two ways to do IPI, ACLINT and IMSIC. One thing that may help us further: Can you clarify on the exact meaning of "M-mode only"? OpenSBI would use PMP to protect those MSWI/MTIMER regions, so I wonder if you meant that it's enforced by the PMP settings, or it's *actually* enforced by the device itself (or fabric)? AFAIK, to achieve this, the device must have a way to distinguish the privilege- level of the CPU at the time it initiated the MMIO request. Hence, the core must be putting the privilege level as some kind of attribute in the MMIO request. Is that the case in k3? Can you confirm with SpacemiT? On 9/8/26 09:28, Junhui Liu wrote: > When testing OpenSBI with the upstream Device Tree, the CLINT controller > failed to function properly with the irqchip.riscv_imsic_noipi boot > parameter: > > Platform IPI Device : aclint-mswi > Platform Timer Device : aclint-mtimer @ 24000000Hz > > Domain0 Region03 : 0x00000000e081c000-0x00000000e081ffff M: (I,R,W) S/U: () > > [ 0.091014] smp: Bringing up secondary CPUs ... > [ 10.104917] CPU1 failed to report alive state > [ 20.118689] CPU2 failed to report alive state > [ 30.132288] CPU3 failed to report alive state > [ 40.145953] CPU4 failed to report alive state > [ 50.159604] CPU5 failed to report alive state > [ 60.173212] CPU6 failed to report alive state > [ 70.186981] CPU7 failed to report alive state > [ 70.191411] smp: Brought up 1 node, 1 CPU > > Through exploring and testing, I discovered that the K3 actually > provides all three complete ACLINT components, and subsequent > confirmation with the vendor yielded the following information: > > The ACLINT controllers are mapped to two physical memory regions: > secure (0xf1810000-0xf1820000) and non-secure (0xe0810000-0xe0820000), > with varying accessibility per controller and execution mode: > > +---------+--------+------------------------+-----------------------+ > | Offset | Module | Secure Region | Non-Secure Region | > +---------+--------+------------------------+-----------------------+ > | +0x0000 | MSWI | 0xf1810000-0xf1813fff | 0xe0810000-0xe0813fff | > | | | (M-mode only) | (Inaccessible) | > +---------+--------+------------------------+-----------------------+ > | +0x4000 | MTIMER | 0xf1814000-0xf181bfff | 0xe0814000-0xe081bfff | > | | | (M-mode only) | (Inaccessible) | > +---------+--------+------------------------+-----------------------+ > | +0xc000 | SSWI | 0xf181c000-0xf181ffff | 0xe081c000-0xe081ffff | > | | | (M-mode only if efused)| (M/S-mode Accessible) | > +---------+--------+------------------------+-----------------------+ > > Taking these constraints into account, we choose the secure region > (0xf1810000-0xf181bfff) for the M-mode ACLINT components (MSWI and > MTIMER), and the non-secure region (0xe081c000-0xe081ffff) for the > S-mode SSWI component. > > Signed-off-by: Junhui Liu > --- > Changes in v2: > - Drop the generic riscv,aclint-* fallback compatibles and use only > SpacemiT K3-specific compatibles. > - Match spacemit,k3-aclint-sswi directly in the SSWI driver. > - Squash the ACLINT MSWI and MTIMER DT additions into the patch that > replaces the incorrect CLINT node. > - Link to v1: https://patch.msgid.link/20260729-k3-aclint-v1-0-aef88614d3a5@pigmoral.tech > > --- > Junhui Liu (6): > dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3 > dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3 > dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3 > dt-bindings: timer: sifive,clint: Deprecate spacemit,k3-clint > irqchip/aclint-sswi: Add support for SpacemiT K3 > riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes > > .../thead,c900-aclint-mswi.yaml | 1 + > .../thead,c900-aclint-sswi.yaml | 5 +-- > .../devicetree/bindings/timer/sifive,clint.yaml | 5 ++- > .../bindings/timer/thead,c900-aclint-mtimer.yaml | 1 + > arch/riscv/boot/dts/spacemit/k3.dtsi | 37 ++++++++++++++++------ > drivers/irqchip/irq-aclint-sswi.c | 1 + > 6 files changed, 37 insertions(+), 13 deletions(-) > --- > base-commit: cee9395acd8043be0644b25c34bfa86623f2b935 > change-id: 20260729-k3-aclint-94ca9d3f818f > > Best regards, > -- > Junhui Liu > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Bo _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv