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Fri, 15 Sep 2023 00:29:56 -0700 (PDT) Received: from [192.168.1.20] ([178.197.214.188]) by smtp.gmail.com with ESMTPSA id c1-20020aa7c981000000b00523653295f9sm1833849edt.94.2023.09.15.00.29.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Sep 2023 00:29:56 -0700 (PDT) Message-ID: <0fbda26b-235e-5043-d83e-af873dada5e5@linaro.org> Date: Fri, 15 Sep 2023 09:29:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH 06/12] dt-bindings: timer: Add Sophgo sg2042 clint Content-Language: en-US To: Wang Chen , linux-riscv@lists.infradead.org, conor@kernel.org, aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, Inochi Amaoto References: <20230915072415.118100-1-wangchen20@iscas.ac.cn> From: Krzysztof Kozlowski In-Reply-To: <20230915072415.118100-1-wangchen20@iscas.ac.cn> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230915_002959_301309_DA8E2A33 X-CRM114-Status: GOOD ( 17.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 15/09/2023 09:24, Wang Chen wrote: > From: Inochi Amaoto > > The timer and ipi(mswi) of sg2042 are on different addresses. With the > same compatible string, this will cause a mismatch when is processed by > SBI. No, same devices (obviously on different addresses) with same programming interface have *the same compatible*. > > Add two new compatible string formatted like `C9xx-clint-xxx` to identify > the timer and ipi device separately, and do not allow c900-clint as the > fallback to avoid conflict. > > Signed-off-by: Inochi Amaoto > --- > .../bindings/timer/sifive,clint.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a0185e15a42f..2a86b80c3f1e 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -39,6 +39,14 @@ properties: > - allwinner,sun20i-d1-clint > - thead,th1520-clint > - const: thead,c900-clint > + - items: > + - enum: > + - sophgo,sg2042-clint-mtimer > + - const: thead,c900-clint-mtimer > + - items: > + - enum: > + - sophgo,sg2042-clint-mswi > + - const: thead,c900-clint-mswi > - items: > - const: sifive,clint0 > - const: riscv,clint0 > @@ -74,4 +82,22 @@ examples: > <&cpu4intc 3>, <&cpu4intc 7>; > reg = <0x2000000 0x10000>; > }; > + - | > + clint-mtimer@ac010000 { > + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; > + interrupts-extended = <&cpu1intc 7>, > + <&cpu2intc 7>, > + <&cpu3intc 7>, > + <&cpu4intc 7>; > + reg = <0xac010000 0x00007ff8>; Drop example, not needed. > + }; > + - | > + clint-mswi@94000000 { > + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; > + interrupts-extended = <&cpu1intc 3>, > + <&cpu2intc 3>, > + <&cpu3intc 3>, > + <&cpu4intc 3>; > + reg = <0x94000000 0x00004000>; Drop example, not needed. > + }; > ... Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv