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Mon, 27 Jun 2022 14:53:44 +0100 MIME-Version: 1.0 Date: Mon, 27 Jun 2022 14:53:44 +0100 From: Marc Zyngier To: Geert Uytterhoeven Cc: "Lad, Prabhakar" , Lad Prabhakar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Linux-Renesas , LKML , Biju Das Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: References: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <87wnd3erab.wl-maz@kernel.org> <87v8snehwi.wl-maz@kernel.org> User-Agent: Roundcube Webmail/1.4.13 Message-ID: <0fdbfdd0ee1c7ca39f8d3e2f86af1194@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: geert@linux-m68k.org, prabhakar.csengg@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_065351_015645_BF7C4595 X-CRM114-Status: GOOD ( 36.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2022-06-27 14:12, Geert Uytterhoeven wrote: > Hi Prabhakar, > > On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar > wrote: >> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven >> wrote: >> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier wrote: >> > > On Sun, 26 Jun 2022 10:38:18 +0100, >> > > "Lad, Prabhakar" wrote: >> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier wrote: >> > > > > On Sun, 26 Jun 2022 01:43:26 +0100, >> > > > > Lad Prabhakar wrote: >> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The >> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In >> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt >> > > > > > edge until the previous completion message has been received and >> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the >> > > > > > interrupts if not acknowledged in time. >> > > > > > >> > > > > > So the workaround for edge-triggered interrupts to be handled correctly >> > > > > > and without losing is that it needs to be acknowledged first and then >> > > > > > handler must be run so that we don't miss on the next edge-triggered >> > > > > > interrupt. >> > > > > > >> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds >> > > > > > support to change interrupt flow based on the interrupt type. It also >> > > > > > implements irq_ack and irq_set_type callbacks. >> > > > > > >> > > > > > Signed-off-by: Lad Prabhakar >> > >> > > > > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { >> > > > > > + priv->of_data = RENESAS_R9A07G043_PLIC; >> > > > > > + plic_chip.name = "Renesas RZ/Five PLIC"; >> > > > > >> > > > > NAK. The irq_chip structure isn't the place for platform marketing. >> > > > > This is way too long anyway (and same for the edge version), and you >> > > > > even sent me a patch to make that structure const... >> > > > > >> > > > My bad will drop this. >> > > >> > > And why you're at it, please turn this rather random 'of_data' into >> > > something like: >> > > >> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c >> > > index bb87e4c3b88e..cd1683b77caf 100644 >> > > --- a/drivers/irqchip/irq-sifive-plic.c >> > > +++ b/drivers/irqchip/irq-sifive-plic.c >> > > @@ -64,6 +64,10 @@ struct plic_priv { >> > > struct cpumask lmask; >> > > struct irq_domain *irqdomain; >> > > void __iomem *regs; >> > > + enum { >> > > + VANILLA_PLIC, >> > > + RENESAS_R9A07G043_PLIC, >> > > + } flavour; >> > > }; >> > > >> > > struct plic_handler { >> > > >> > > to give some structure to the whole thing, because I'm pretty sure >> > > we'll see more braindead implementations as time goes by. >> > >> > What about using a feature flag (e.g. had_edge_irqs) instead? >> >> diff --git a/drivers/irqchip/irq-sifive-plic.c >> b/drivers/irqchip/irq-sifive-plic.c >> index 9f16833dcb41..247c3c98b655 100644 >> --- a/drivers/irqchip/irq-sifive-plic.c >> +++ b/drivers/irqchip/irq-sifive-plic.c >> @@ -60,13 +60,13 @@ >> #define PLIC_DISABLE_THRESHOLD 0x7 >> #define PLIC_ENABLE_THRESHOLD 0 >> >> +#define PLIC_QUIRK_EDGE_INTERRUPT BIT(0) >> >> struct plic_priv { >> struct cpumask lmask; >> struct irq_domain *irqdomain; >> void __iomem *regs; >> + u32 plic_quirks; >> }; >> >> What about something like above? > > LGTM. > > Marc suggested to make this unsigned long, but TBH, that won't make > much of a difference. PLICs are present on RV32 SoCs, too, so you > cannot rely on having more than 32 bits anyway. But it will make a difference on a 64bit platform, as we want to use test_bit() and co to check for features. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv