From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44558C433F5 for ; Fri, 7 Oct 2022 09:22:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h5hIc2mbn63rnlxmv8OggcaCdPcMyNIL0lqciTtGgGE=; b=Oo7NK6lbi+GXL6 7JaInWafG3qrWMbSmDDPFQTIVa/5/SRrMKT8E6ZaD6gIDxQZueHqPTpauE6St3XIAvAgM2yANixv/ SKo6vbQZMN4fYGwQyygV4X2JYN6x7liMSft1r/TgNkEvctK47tBUWG9nsey7b4Bie3NAe4tLw9CHB mpKwoFE/+vK8MJHsyY9YUVKhsx2BN/zUcOnLkfYOc9eDWrFlc8Qh/DOsfieMHp84nkhBkRHk1nmOY jvKpngWFL59H8VYnw0Sgjkt5k3RScu+izERLK0LSSLMjDBfl1FqJVrTdh3VPwpmxQBFAaEsxz7Woi eJyEFfHpcMkMY52ABkNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ogjYc-008HXm-Lw; Fri, 07 Oct 2022 09:22:14 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ogjYa-008HXH-EH for linux-riscv@lists.infradead.org; Fri, 07 Oct 2022 09:22:13 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ogjYY-00063C-EQ; Fri, 07 Oct 2022 11:22:10 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Jisheng Zhang Subject: Re: [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Date: Fri, 07 Oct 2022 11:22:09 +0200 Message-ID: <13539612.RDIVbhacDa@diego> In-Reply-To: <20221006070818.3616-4-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> <20221006070818.3616-4-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221007_022212_505228_A8411690 X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Am Donnerstag, 6. Oktober 2022, 09:08:13 CEST schrieb Jisheng Zhang: > We will make use of ISA extension in asm files, so make the multi-letter > RISC-V ISA extension IDs macros rather than enums and move them and > those base ISA extension IDs to suitable place. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/hwcap.h | 45 +++++++++++++++++----------------- > 1 file changed, 23 insertions(+), 22 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 6f59ec64175e..6cf445653911 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -12,20 +12,6 @@ > #include > #include > > -#ifndef __ASSEMBLY__ > -#include > -/* > - * This yields a mask that user programs can use to figure out what > - * instruction set this cpu supports. > - */ > -#define ELF_HWCAP (elf_hwcap) > - > -enum { > - CAP_HWCAP = 1, > -}; > - > -extern unsigned long elf_hwcap; > - > #define RISCV_ISA_EXT_a ('a' - 'a') > #define RISCV_ISA_EXT_c ('c' - 'a') > #define RISCV_ISA_EXT_d ('d' - 'a') > @@ -46,21 +32,36 @@ extern unsigned long elf_hwcap; > #define RISCV_ISA_EXT_BASE 26 > > /* > - * This enum represent the logical ID for each multi-letter RISC-V ISA extension. > + * These macros represent the logical ID for each multi-letter RISC-V ISA extension. > * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed > * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter > * extensions while all the multi-letter extensions should define the next > * available logical extension id. > */ > -enum riscv_isa_ext_id { > - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > - RISCV_ISA_EXT_SVPBMT, > - RISCV_ISA_EXT_ZICBOM, > - RISCV_ISA_EXT_ZIHINTPAUSE, > - RISCV_ISA_EXT_SSTC, > - RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > +#define RISCV_ISA_EXT_SSCOFPMF 26 > +#define RISCV_ISA_EXT_SVPBMT 27 > +#define RISCV_ISA_EXT_ZICBOM 28 > +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 > +#define RISCV_ISA_EXT_SSTC 30 > + > +#define RISCV_ISA_EXT_ID_MAX RISCV_ISA_EXT_MAX > + > + nit: double empty line > +#ifndef __ASSEMBLY__ > +#include > +/* > + * This yields a mask that user programs can use to figure out what > + * instruction set this cpu supports. > + */ > +#define ELF_HWCAP (elf_hwcap) > + > +enum { > + CAP_HWCAP = 1, > }; > > +extern unsigned long elf_hwcap; > + > + nit: double empty line, otherwise Reviewed-by: Heiko Stuebner > /* > * This enum represents the logical ID for each RISC-V ISA extension static > * keys. We can use static key to optimize code path if some ISA extensions > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv