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From: zong@andestech.com (Zong Li)
To: linux-riscv@lists.infradead.org
Subject: [PATCH] RISC-V: Add conditional marco for boot_sec_cpu
Date: Thu, 21 Jun 2018 09:41:42 +0800	[thread overview]
Message-ID: <1529545326-29272-1-git-send-email-zong@andestech.com> (raw)
In-Reply-To: <cover.1529506497.git.zong@andestech.com>

Fix link error when disable support SMP.
It causes the undefined reference to `smp_callin'.

Signed-off-by: Zong Li <zong@andestech.com>
---
 arch/riscv/kernel/head.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 3b6293f10e3e..396ec7b349ce 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -152,6 +152,7 @@ END(_start)
 .section .text
 .global boot_sec_cpu
 
+#ifdef CONFIG_HOTPLUG_CPU
 boot_sec_cpu:
 	/* clear all pending flags */
 	csrw sip, zero
@@ -160,6 +161,7 @@ boot_sec_cpu:
 	fence
 
 	tail smp_callin
+#endif
 
 __PAGE_ALIGNED_BSS
 	/* Empty zero page */
-- 
2.16.1

  parent reply	other threads:[~2018-06-21  1:41 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-21  1:41 [PATCH 0/5] Building for 32-bit RISC-V kernel Zong Li
2018-06-21  1:41 ` [PATCH 1/5] RISC-V: Add conditional macro for zone of DMA32 Zong Li
2018-06-21  6:40   ` Christoph Hellwig
2018-06-21  7:06     ` Zong Li
2018-06-21  1:41 ` Zong Li [this message]
2018-06-21  1:41 ` [PATCH 2/5] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li
2018-06-21  1:41 ` [PATCH 3/5] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li
2018-06-21  1:41 ` [PATCH 4/5] RISC-V: Change variable type for 32-bit compatible Zong Li
2018-06-21  6:41   ` Christoph Hellwig
2018-06-21  7:12     ` Zong Li
2018-06-21 15:19       ` Zong Li
2018-06-21  1:41 ` [PATCH 5/5] RISC-V: Use fixed width integer types " Zong Li
2018-06-21  6:43   ` Christoph Hellwig
2018-06-21 10:13     ` Zong Li
2018-06-21 10:21     ` Andreas Schwab
2018-06-21 14:53       ` Christoph Hellwig

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