* [PATCH v2] RISC-V: Add the directive for alignment of stvec's value
@ 2018-08-02 15:21 Zong Li
[not found] ` <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com>
0 siblings, 1 reply; 3+ messages in thread
From: Zong Li @ 2018-08-02 15:21 UTC (permalink / raw)
To: linux-riscv
The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.
Signed-off-by: Zong Li <zong@andestech.com>
---
arch/riscv/kernel/head.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 3b6293f..11066d5 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -94,6 +94,7 @@ relocate:
or a0, a0, a1
sfence.vma
csrw sptbr, a0
+.align 2
1:
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
@@ -143,6 +144,7 @@ relocate:
tail smp_callin
#endif
+.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread[parent not found: <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com>]
* FW: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value [not found] ` <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com> @ 2018-08-10 0:37 ` Zong Li 2018-08-10 1:50 ` Palmer Dabbelt 0 siblings, 1 reply; 3+ messages in thread From: Zong Li @ 2018-08-10 0:37 UTC (permalink / raw) To: linux-riscv > Subject: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value > > The stvec's value must be 4 byte alignment by specification definition. > These directives avoid to stvec be set the non-alignment value. > > Signed-off-by: Zong Li <zong@andestech.com> > --- > arch/riscv/kernel/head.S | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f..11066d5 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -94,6 +94,7 @@ relocate: > or a0, a0, a1 > sfence.vma > csrw sptbr, a0 > +.align 2 > 1: > /* Set trap vector to spin forever to help debug */ > la a0, .Lsecondary_park > @@ -143,6 +144,7 @@ relocate: > tail smp_callin > #endif > > +.align 2 > .Lsecondary_park: > /* We lack SMP support or have too many harts, so park this hart */ > wfi ping ^ permalink raw reply [flat|nested] 3+ messages in thread
* FW: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value 2018-08-10 0:37 ` FW: " Zong Li @ 2018-08-10 1:50 ` Palmer Dabbelt 0 siblings, 0 replies; 3+ messages in thread From: Palmer Dabbelt @ 2018-08-10 1:50 UTC (permalink / raw) To: linux-riscv On Thu, 09 Aug 2018 17:37:39 PDT (-0700), zongbox at gmail.com wrote: >> Subject: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value >> >> The stvec's value must be 4 byte alignment by specification definition. >> These directives avoid to stvec be set the non-alignment value. >> >> Signed-off-by: Zong Li <zong@andestech.com> >> --- >> arch/riscv/kernel/head.S | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f..11066d5 100644 >> --- a/arch/riscv/kernel/head.S >> +++ b/arch/riscv/kernel/head.S >> @@ -94,6 +94,7 @@ relocate: >> or a0, a0, a1 >> sfence.vma >> csrw sptbr, a0 >> +.align 2 >> 1: >> /* Set trap vector to spin forever to help debug */ >> la a0, .Lsecondary_park >> @@ -143,6 +144,7 @@ relocate: >> tail smp_callin >> #endif >> >> +.align 2 >> .Lsecondary_park: >> /* We lack SMP support or have too many harts, so park this hart */ >> wfi Thanks, this got lost in the shuffle somewhere. It's in for-next now. ^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-08-02 15:21 [PATCH v2] RISC-V: Add the directive for alignment of stvec's value Zong Li
[not found] ` <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com>
2018-08-10 0:37 ` FW: " Zong Li
2018-08-10 1:50 ` Palmer Dabbelt
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