Re: [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators

Heiko Stübner
2022-08-24T17:42:14Z

Am Dienstag, 23. August 2022, 20:33:19 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The QEMU virt and spike machines currently export a riscv,isa string of
> "rv64imafdcsuh",
>
> While the RISC-V foundation has been ratifying a bunch of extenstions
> etc, the kernel has remained relatively static with what hardware is
> supported - but the same is not true of QEMU. Using the virt machine
> and running dt-validate on the dumped dtb fails, partly due to the
> unexpected isa string.
>
> Rather than enumerate the many many possbilities, change the pattern
> to a regex, with the following assumptions:
> - ima are required
> - the single letter order is fixed & we don't care about things that
> can't even do "ima"
> - the standard multi letter extensions are all in a "_z<foo>" format
> where the first letter of <foo> is a valid single letter extension
> - _s & _h are used for supervisor and hyper visor extensions
> - convention says that after the first two chars, a standard multi
> letter extension name could be an english word (ifencei anyone?) so
> it's not worth restricting the charset
> - as the above is just convention, don't apply any charset restrictions
> to reduce future churn
> - vendor ISA extensions begind with _x and have no charset restrictions
> - we don't care about an e extension from an OS pov
> - that attempting to validate the contents of the multiletter extensions
> with dt-validate beyond the formatting is a futile, massively verbose
> or unwieldy exercise at best
>
> The following limitations also apply:
> - multi letter extension ordering is not enforced. dt-schema does not
> appear to allow for named match groups, so the resulting regex would
> be even more of a headache
> - ditto for the numbered extensions

That description sounds about right, though me and regexes never
became friends, so the following will have to do:

Acked-by: Heiko Stuebner <heiko@sntech.de>

> Finally, add me as a maintainer of the binding so that when it breaks
> in the future, I can be held responsible!
>
> Reported-by: Rob Herring <robh@kernel.org>
> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Palmer, feel free to drop the maintainer addition. I just mostly want
> to clean up my own mess on this when they decide to ratify more
> extensions & this comes back up again.
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..90a7cabf58fe 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -9,6 +9,7 @@ title: RISC-V bindings for 'cpus' DT nodes
> maintainers:
> - Paul Walmsley <paul.walmsley@sifive.com>
> - Palmer Dabbelt <palmer@sifive.com>
> + - Conor Dooley <conor@kernel.org>
>
> description: |
> This document uses some terminology common to the RISC-V community
> @@ -79,9 +80,7 @@ properties:
> insensitive, letters in the riscv,isa string must be all
> lowercase to simplify parsing.
> $ref: "/schemas/types.yaml#/definitions/string"
> - enum:
> - - rv64imac
> - - rv64imafdc
> + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
>
> # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
> timebase-frequency: false