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b=eaEtbOMu4nfKW+FhSRPDP4KCoeV3yqjOYev8iwOd7KS/u7vrORhIJ4U/bNK/ob9Ov u30Qc9Zz56xiClFlaRxduKiBwoSah7ZKwpvQMa2SuJhe//h50v3P+3g5T6dx7RRAIL 6cIgodlg/2/CgZEoyKwxPgN1h4V8aSCHybAnz1Mfrg3f4taKpB7WTYXwHvaKMuzJIX IinuSTMetR0WPZuBg5IF18Q71bVGaWVDqyYQsEr5pPGDK6otGw/iS+mS88ya+845kN i/XRCNRuzUWiHTM94zaMnM6BZebYS7Zed7+o+ZLJDz5T0iq5rsFrYgd2cSkaX1CY77 0V609usuYiX2w== Received: from aws-us-west-2-korg-oddjob-1.ci.codeaurora.org (localhost.localdomain [127.0.0.1]) by aws-us-west-2-korg-oddjob-1.ci.codeaurora.org (Postfix) with ESMTP id 99F7FC43143; Sun, 25 Jun 2023 23:20:23 +0000 (UTC) MIME-Version: 1.0 Subject: Re: [PATCH v3 0/7] ISA string parser cleanups From: patchwork-bot+linux-riscv@kernel.org Message-Id: <168773522362.24181.16156078607515411409.git-patchwork-notify@kernel.org> Date: Sun, 25 Jun 2023 23:20:23 +0000 References: <20230607-audacity-overhaul-82bb867a825f@spud> In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> To: Conor Dooley Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com, devicetree@vger.kernel.org, robh+dt@kernel.org, cyy@cyyself.name, conor.dooley@microchip.com, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, ajones@ventanamicro.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230625_162025_977165_22805725 X-CRM114-Status: GOOD ( 19.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt : On Wed, 7 Jun 2023 21:28:24 +0100 you wrote: > From: Conor Dooley > > With that out of the way, here are some cleanups for our riscv,isa > handling. > > Here are some bits that were discussed with Drew on the "should we > allow caps" threads that I have now created patches for: > - splitting of riscv_of_processor_hartid() into two distinct functions, > one for use purely during early boot, prior to the establishment of > the possible-cpus mask & another to fit the other current use-cases > - that then allows us to then completely skip some validation of the > hartid in the parser > - the biggest diff in the series is a rework of the comments in the > parser, as I have mostly found the existing (sparse) ones to not be > all that helpful whenever I have to go back and look at it > - from writing the comments, I found a conditional doing a bit of a > dance that I found counter-intuitive, so I've had a go at making that > match what I would expect a little better > - `i` implies 4 other extensions, so add them as extensions and set > them for the craic. Sure why not like... > > [...] Here is the summary with links: - [v3,1/7] RISC-V: simplify register width check in ISA string parsing https://git.kernel.org/riscv/c/fed14be476f0 - [v3,2/7] RISC-V: split early & late of_node to hartid mapping https://git.kernel.org/riscv/c/2ac874343749 - [v3,3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing https://git.kernel.org/riscv/c/069b0d517077 - [v3,4/7] RISC-V: rework comments in ISA string parser https://git.kernel.org/riscv/c/6b913e3da87d - [v3,5/7] RISC-V: remove decrement/increment dance in ISA string parser https://git.kernel.org/riscv/c/7816ebc1ddd1 - [v3,6/7] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support https://git.kernel.org/riscv/c/1e5cae98e46d - [v3,7/7] RISC-V: always report presence of extensions formerly part of the base ISA https://git.kernel.org/riscv/c/07edc32779e3 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv