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Thu, 2 Nov 2023 20:20:30 +0000 (UTC) MIME-Version: 1.0 Subject: Re: [PATCH 0/5] Enable peripherals on RZ/Five SMARC EVK From: patchwork-bot+linux-riscv@kernel.org Message-Id: <169895643051.22248.10364642768194481579.git-patchwork-notify@kernel.org> Date: Thu, 02 Nov 2023 20:20:30 +0000 References: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> To: Lad@ci.codeaurora.org, Prabhakar Cc: linux-riscv@lists.infradead.org, geert+renesas@glider.be, magnus.damm@gmail.com, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231102_132033_407136_521A6C8B X-CRM114-Status: GOOD ( 10.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt : On Fri, 29 Sep 2023 01:06:59 +0100 you wrote: > From: Lad Prabhakar > > Hi All, > > This patch series does the following: > * Adds L2 cache node and marks the SoC as noncoherent > * Enables IP blocks which were explicitly disabled and for > which support is present > * Enables the configs required for RZ/Five SoC > > [...] Here is the summary with links: - [1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node (no matching commit) - [2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property (no matching commit) - [3/5] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled (no matching commit) - [4/5] riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node (no matching commit) - [5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC https://git.kernel.org/riscv/c/db38228c03d6 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv