From: patchwork-bot+linux-riscv@kernel.org
To: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2VyIDxjbGVnZXJAcml2b3NpbmMuY29tPg==?=@ci.codeaurora.org
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: fix misaligned access handling of C.SWSP and C.SDSP
Date: Thu, 07 Dec 2023 15:20:25 +0000 [thread overview]
Message-ID: <170196242582.12999.14639879842015285303.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20231103090223.702340-1-cleger@rivosinc.com>
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Fri, 3 Nov 2023 10:02:23 +0100 you wrote:
> This is a backport of a fix that was done in OpenSBI: ec0559eb315b
> ("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP").
>
> Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
> register, so checking that the rs2 field is non-zero is unnecessary.
>
> Additionally, the previous check was incorrect since it was checking
> the immediate field of the instruction instead of the rs2 field.
>
> [...]
Here is the summary with links:
- riscv: fix misaligned access handling of C.SWSP and C.SDSP
https://git.kernel.org/riscv/c/22e0eb04837a
You are awesome, thank you!
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prev parent reply other threads:[~2023-12-07 15:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-03 9:02 [PATCH] riscv: fix misaligned access handling of C.SWSP and C.SDSP Clément Léger
2023-12-07 15:20 ` patchwork-bot+linux-riscv [this message]
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