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From: "Heiko Stübner" <heiko@sntech.de>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	linux-riscv@lists.infradead.org
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	Tsukasa OI <research_trasio@irq.a4lg.com>
Subject: Re: [PATCH v3 1/3] RISC-V: Correctly print supported extensions
Date: Mon, 14 Feb 2022 21:04:07 +0100	[thread overview]
Message-ID: <1722531.ZnnOanGknH@diego> (raw)
In-Reply-To: <d4d5a22e24d477ab4d8284d0140e17c6c5ff5464.1644647398.git.research_trasio@irq.a4lg.com>

Am Samstag, 12. Februar 2022, 07:29:59 CET schrieb Tsukasa OI:
> This commit replaces BITS_PER_LONG with number of alphabet letters.
> 
> Current ISA pretty-printing code expects extension 'a' (bit 0) through
> 'z' (bit 25).  Although bit 26 and higher is not currently used (thus never
> cause an issue in practice), it will be an annoying problem if we start to
> use those in the future.
> 
> This commit disables printing high bits for now.
> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Tested-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  arch/riscv/kernel/cpufeature.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index d959d207a40d..dd3d57eb4eea 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -13,6 +13,8 @@
>  #include <asm/smp.h>
>  #include <asm/switch_to.h>
>  
> +#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
> +
>  unsigned long elf_hwcap __read_mostly;
>  
>  /* Host ISA bitmap */
> @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void)
>  {
>  	struct device_node *node;
>  	const char *isa;
> -	char print_str[BITS_PER_LONG + 1];
> +	char print_str[NUM_ALPHA_EXTS + 1];
>  	size_t i, j, isa_len;
>  	static unsigned long isa2hwcap[256] = {0};
>  
> @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void)
>  	}
>  
>  	memset(print_str, 0, sizeof(print_str));
> -	for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> +	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
>  		if (riscv_isa[0] & BIT_MASK(i))
>  			print_str[j++] = (char)('a' + i);
>  	pr_info("riscv: ISA extensions %s\n", print_str);
>  
>  	memset(print_str, 0, sizeof(print_str));
> -	for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> +	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
>  		if (elf_hwcap & BIT_MASK(i))
>  			print_str[j++] = (char)('a' + i);
>  	pr_info("riscv: ELF capabilities %s\n", print_str);
> 
> base-commit: 7aed1489bdf879da403e8ee9d6d77b0be26bb84d
> 





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  reply	other threads:[~2022-02-14 20:04 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-10 21:40 [PATCH v2 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-02-10 21:40 ` [PATCH v2 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-02-10 21:40 ` [PATCH v2 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-02-12  6:25   ` Tsukasa OI
2022-02-12  6:29     ` [PATCH v3 1/3] RISC-V: Correctly print supported extensions Tsukasa OI
2022-02-14 20:04       ` Heiko Stübner [this message]
2022-02-12  6:30     ` [PATCH v3 2/3] RISC-V: Minimal parser for "riscv, isa" strings Tsukasa OI
2022-02-14 20:04       ` Heiko Stübner
2022-02-12  6:30     ` [PATCH v3 3/3] RISC-V: Extract multi-letter extension names from "riscv, isa" Tsukasa OI
2022-02-14 20:04       ` Heiko Stübner
2022-02-14 20:07     ` [PATCH v2 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-02-15  3:27       ` Tsukasa OI
2022-02-15  7:36         ` Atish Patra
2022-02-10 21:40 ` [PATCH v2 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-02-10 21:40 ` [PATCH v2 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-02-14 20:05   ` Heiko Stübner
2022-02-14 20:14     ` Atish Patra
2022-02-14 20:24       ` Heiko Stübner
2022-02-14 20:42         ` Atish Patra
2022-02-14 22:22           ` Heiko Stübner
2022-02-14 23:22             ` Atish Kumar Patra
2022-02-15  9:12               ` Atish Kumar Patra
2022-02-15  9:48                 ` Heiko Stübner
2022-02-15  9:50                   ` Heiko Stübner
2022-02-16  0:47                     ` Atish Kumar Patra
2022-02-10 21:40 ` [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
2022-02-10 21:58   ` Andreas Schwab
2022-02-11 12:52     ` Geert Uytterhoeven
2022-02-14 20:15       ` Atish Patra
2022-02-14 20:06   ` Heiko Stübner
2022-02-10 21:40 ` [PATCH v2 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-02-14 20:07   ` Heiko Stübner

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