From: patchwork-bot+linux-riscv@kernel.org
To: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Cc: linux-riscv@lists.infradead.org, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
conor.dooley@microchip.com, djordje.todorovic@htecgroup.com,
linux-kernel@vger.kernel.org, cfu@wavecomp.com
Subject: Re: [PATCH v2] riscv: Update MIPS vendor id to 0x127.
Date: Mon, 17 Nov 2025 08:10:30 +0000 [thread overview]
Message-ID: <176336703025.2854411.5259093565399811125.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20251113-mips-vendorid-v2-1-3279489b7f84@htecgroup.com>
Hello:
This patch was applied to riscv/linux.git (fixes)
by Paul Walmsley <pjw@kernel.org>:
On Thu, 13 Nov 2025 17:10:32 +0100 you wrote:
> From: Chao-ying Fu <cfu@wavecomp.com>
>
> [1] defines MIPS vendor id as 0x127. All previous MIPS RISC-V patches
> were tested on QEMU, also modified to use 0x722 as MIPS_VENDOR_ID. This
> new value should reflect real hardware.
>
> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
>
> [...]
Here is the summary with links:
- [v2] riscv: Update MIPS vendor id to 0x127.
https://git.kernel.org/riscv/c/91f815b7073d
You are awesome, thank you!
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prev parent reply other threads:[~2025-11-17 8:11 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-13 16:10 [PATCH v2] riscv: Update MIPS vendor id to 0x127 Aleksa Paunovic via B4 Relay
2025-11-17 8:10 ` patchwork-bot+linux-riscv [this message]
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