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From: patchwork-bot+linux-riscv@kernel.org
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: linux-riscv@lists.infradead.org, alex@ghiti.fr,
	aou@eecs.berkeley.edu, iommu@lists.linux.dev, joro@8bytes.org,
	palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com,
	will@kernel.org, ajones@ventanamicro.com, jroedel@suse.de,
	lihangjing@bytedance.com, luxu.kernel@bytedance.com,
	patches@lists.linux.dev, tjeznach@rivosinc.com,
	vincent.chen@sifive.com, xieyongji@bytedance.com
Subject: Re: [PATCH v4 0/6] Convert riscv to use the generic iommu page table
Date: Thu, 30 Apr 2026 03:25:07 +0000	[thread overview]
Message-ID: <177751950779.2274119.4057431786381222118.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <0-v4-5a9ca1a9b7a5+5f2-iommu_pt_riscv_jgg@nvidia.com>

Hello:

This series was applied to riscv/linux.git (fixes)
by Joerg Roedel <joerg.roedel@amd.com>:

On Fri, 27 Feb 2026 11:25:35 -0400 you wrote:
> This is a fairly straightforward conversion of the RISC-V iommu driver to
> use the now merged generic iommu page table code.
> 
> It brings support for SVNAPOT which is a 64K contiguous page. Otherwise it
> should not change the behavior.
> 
> The series disables SADE as the dirty tracking support is not implemented
> in the driver and should be done somewhat differently. The generic code
> gets further along though this does not include the format implementation
> of read and clear dirty.
> 
> [...]

Here is the summary with links:
  - [v4,1/6] iommupt: Add the RISC-V page table format
    https://git.kernel.org/riscv/c/e71e00127110
  - [v4,2/6] iommu/riscv: Disable SADE
    https://git.kernel.org/riscv/c/e93e4a6363b8
  - [v4,3/6] iommu/riscv: Use the generic iommu page table
    https://git.kernel.org/riscv/c/e5ef32191a87
  - [v4,4/6] iommu/riscv: Enable SVNAPOT support for contiguous ptes
    https://git.kernel.org/riscv/c/69541898b71a
  - [v4,5/6] iommu/riscv: Add missing GENERIC_MSI_IRQ
    https://git.kernel.org/riscv/c/c70d20b25ca3
  - [v4,6/6] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST
    https://git.kernel.org/riscv/c/7cd0c655f02f

You are awesome, thank you!
-- 
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      parent reply	other threads:[~2026-04-30  3:26 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-27 15:25 [PATCH v4 0/6] Convert riscv to use the generic iommu page table Jason Gunthorpe
2026-02-27 15:25 ` [PATCH v4 1/6] iommupt: Add the RISC-V page table format Jason Gunthorpe
2026-02-27 15:25 ` [PATCH v4 2/6] iommu/riscv: Disable SADE Jason Gunthorpe
2026-02-27 15:25 ` [PATCH v4 3/6] iommu/riscv: Use the generic iommu page table Jason Gunthorpe
2026-02-27 15:25 ` [PATCH v4 4/6] iommu/riscv: Enable SVNAPOT support for contiguous ptes Jason Gunthorpe
2026-02-27 15:25 ` [PATCH v4 5/6] iommu/riscv: Add missing GENERIC_MSI_IRQ Jason Gunthorpe
2026-02-27 15:25 ` [PATCH v4 6/6] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST Jason Gunthorpe
2026-03-17 12:14 ` [PATCH v4 0/6] Convert riscv to use the generic iommu page table Joerg Roedel
2026-04-30  3:25 ` patchwork-bot+linux-riscv [this message]

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