From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F141C3DA6E for ; Thu, 28 Dec 2023 09:47:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Us6nID4H1tCivaenvLMoEdJiHSP6VisblVN3auZawMw=; b=X0kPSJtj651Ovr 4fD3h9h65lJ6+ZGIF3LusztRog0F5XBUbXlfMm/Qdl3n/aDyevrQDC0HbHLlIb1z8/6httDa78BqW PHW0OCRUknchZSJDkzUJGbwiFseOEybD4BF8rb0vSEcj2nHnwmqJn4FoY7NcznI7nR1WhJGmjmVcY kV6PyQ+FdAgzk5thIA9wnaMA24WcbN2XjOPuq/y0wx5mymi8aeM4eQqWDT7YR10AY++OPdPz5T1or IWu9AGwTNxkKw5c17nRwq1BnpbpEYZtd+/UBY2ds+CvtIifBnRqXYabJbunbnEaFE74igF8ZgfNip nLa69DYF8vVLH/wYlnQQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rImym-00GVJr-09; Thu, 28 Dec 2023 09:47:04 +0000 Received: from fd01.gateway.ufhost.com ([61.152.239.71]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rImyh-00GVA2-1D for linux-riscv@lists.infradead.org; Thu, 28 Dec 2023 09:47:02 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D6DF07FDC; Thu, 28 Dec 2023 17:46:11 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 28 Dec 2023 17:46:11 +0800 Received: from [192.168.125.85] (183.27.97.107) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 28 Dec 2023 17:46:10 +0800 Message-ID: <196e61f9-2beb-413f-b2fd-4cd8e347ad60@starfivetech.com> Date: Thu, 28 Dec 2023 17:46:09 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 09/21] PCI: microchip: Move setup functions to pcie-plda-host.c Content-Language: en-US To: Lorenzo Pieralisi CC: Conor Dooley , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Daire McNamara , "Emil Renner Berthing" , Krzysztof Kozlowski , , , , , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , "Philipp Zabel" , Mason Huo , Leyfoon Tan , Kevin Xie References: <20231214072839.2367-1-minda.chen@starfivetech.com> <20231214072839.2367-10-minda.chen@starfivetech.com> From: Minda Chen In-Reply-To: X-Originating-IP: [183.27.97.107] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231228_014659_918080_C4DE426C X-CRM114-Status: GOOD ( 19.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2023/12/27 23:49, Lorenzo Pieralisi wrote: > On Thu, Dec 14, 2023 at 03:28:27PM +0800, Minda Chen wrote: >> Move setup functions to common pcie-plda-host.c. So these two functions >> can be re-used. >> >> Signed-off-by: Minda Chen >> Reviewed-by: Conor Dooley >> --- >> drivers/pci/controller/plda/Kconfig | 4 + >> drivers/pci/controller/plda/Makefile | 1 + >> .../pci/controller/plda/pcie-microchip-host.c | 59 -------------- >> drivers/pci/controller/plda/pcie-plda-host.c | 80 +++++++++++++++++++ >> drivers/pci/controller/plda/pcie-plda.h | 5 ++ >> 5 files changed, 90 insertions(+), 59 deletions(-) >> create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c >> >> diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig >> index 5cb3be4fc98c..e54a82ee94f5 100644 >> --- a/drivers/pci/controller/plda/Kconfig >> +++ b/drivers/pci/controller/plda/Kconfig >> @@ -3,10 +3,14 @@ >> menu "PLDA-based PCIe controllers" >> depends on PCI >> >> +config PCIE_PLDA_HOST >> + bool >> + >> config PCIE_MICROCHIP_HOST >> tristate "Microchip AXI PCIe controller" >> depends on PCI_MSI && OF >> select PCI_HOST_COMMON >> + select PCIE_PLDA_HOST >> help >> Say Y here if you want kernel to support the Microchip AXI PCIe >> Host Bridge driver. >> diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile >> index e1a265cbf91c..4340ab007f44 100644 >> --- a/drivers/pci/controller/plda/Makefile >> +++ b/drivers/pci/controller/plda/Makefile >> @@ -1,2 +1,3 @@ >> # SPDX-License-Identifier: GPL-2.0 >> +obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o >> obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o >> diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c >> index 31ca8d44ee2a..2e79bcc7c0a5 100644 >> --- a/drivers/pci/controller/plda/pcie-microchip-host.c >> +++ b/drivers/pci/controller/plda/pcie-microchip-host.c >> @@ -838,65 +838,6 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) >> return mc_allocate_msi_domains(port); >> } >> >> -static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, >> - phys_addr_t axi_addr, phys_addr_t pci_addr, >> - size_t size) >> -{ >> - u32 atr_sz = ilog2(size) - 1; >> - u32 val; >> - >> - if (index == 0) >> - val = PCIE_CONFIG_INTERFACE; >> - else >> - val = PCIE_TX_RX_INTERFACE; >> - >> - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> - ATR0_AXI4_SLV0_TRSL_PARAM); >> - >> - val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | >> - ATR_IMPL_ENABLE; >> - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> - ATR0_AXI4_SLV0_SRCADDR_PARAM); >> - >> - val = upper_32_bits(axi_addr); >> - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> - ATR0_AXI4_SLV0_SRC_ADDR); >> - >> - val = lower_32_bits(pci_addr); >> - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> - ATR0_AXI4_SLV0_TRSL_ADDR_LSB); >> - >> - val = upper_32_bits(pci_addr); >> - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> - ATR0_AXI4_SLV0_TRSL_ADDR_UDW); >> - >> - val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); >> - val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); >> - writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); >> - writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); >> -} >> - >> -static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, >> - struct plda_pcie_rp *port) >> -{ >> - void __iomem *bridge_base_addr = port->bridge_addr; >> - struct resource_entry *entry; >> - u64 pci_addr; >> - u32 index = 1; >> - >> - resource_list_for_each_entry(entry, &bridge->windows) { >> - if (resource_type(entry->res) == IORESOURCE_MEM) { >> - pci_addr = entry->res->start - entry->offset; >> - plda_pcie_setup_window(bridge_base_addr, index, >> - entry->res->start, pci_addr, >> - resource_size(entry->res)); >> - index++; >> - } >> - } >> - >> - return 0; >> -} >> - >> static inline void mc_clear_secs(struct mc_pcie *port) >> { >> void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; >> diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c >> new file mode 100644 >> index 000000000000..19131181897f >> --- /dev/null >> +++ b/drivers/pci/controller/plda/pcie-plda-host.c >> @@ -0,0 +1,80 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PLDA PCIe XpressRich host controller driver >> + * >> + * Copyright (C) 2023 Microchip Co. Ltd >> + * >> + * Author: Daire McNamara >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > Do you really require these headers ? Not in this patch, > in later patches and that's why every header should be > added when it is really needed. > > Lorenzo > OK, I will change this. thanks. >> + >> +#include "pcie-plda.h" >> + >> +void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, >> + phys_addr_t axi_addr, phys_addr_t pci_addr, >> + size_t size) >> +{ >> + u32 atr_sz = ilog2(size) - 1; >> + u32 val; >> + >> + if (index == 0) >> + val = PCIE_CONFIG_INTERFACE; >> + else >> + val = PCIE_TX_RX_INTERFACE; >> + >> + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> + ATR0_AXI4_SLV0_TRSL_PARAM); >> + >> + val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | >> + ATR_IMPL_ENABLE; >> + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> + ATR0_AXI4_SLV0_SRCADDR_PARAM); >> + >> + val = upper_32_bits(axi_addr); >> + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> + ATR0_AXI4_SLV0_SRC_ADDR); >> + >> + val = lower_32_bits(pci_addr); >> + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> + ATR0_AXI4_SLV0_TRSL_ADDR_LSB); >> + >> + val = upper_32_bits(pci_addr); >> + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + >> + ATR0_AXI4_SLV0_TRSL_ADDR_UDW); >> + >> + val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); >> + val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); >> + writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); >> + writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); >> +} >> +EXPORT_SYMBOL_GPL(plda_pcie_setup_window); >> + >> +int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, >> + struct plda_pcie_rp *port) >> +{ >> + void __iomem *bridge_base_addr = port->bridge_addr; >> + struct resource_entry *entry; >> + u64 pci_addr; >> + u32 index = 1; >> + >> + resource_list_for_each_entry(entry, &bridge->windows) { >> + if (resource_type(entry->res) == IORESOURCE_MEM) { >> + pci_addr = entry->res->start - entry->offset; >> + plda_pcie_setup_window(bridge_base_addr, index, >> + entry->res->start, pci_addr, >> + resource_size(entry->res)); >> + index++; >> + } >> + } >> + >> + return 0; >> +} >> +EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); >> diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h >> index 363fcbbaf6ec..3deefd35fa5a 100644 >> --- a/drivers/pci/controller/plda/pcie-plda.h >> +++ b/drivers/pci/controller/plda/pcie-plda.h >> @@ -120,4 +120,9 @@ struct plda_pcie_rp { >> void __iomem *bridge_addr; >> }; >> >> +void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, >> + phys_addr_t axi_addr, phys_addr_t pci_addr, >> + size_t size); >> +int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, >> + struct plda_pcie_rp *port); >> #endif >> -- >> 2.17.1 >> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv