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From: Heiko Stuebner <heiko@sntech.de>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Heiko Stübner" <heiko@sntech.de>
Subject: Re: [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions
Date: Thu, 13 Oct 2022 15:28:57 +0200	[thread overview]
Message-ID: <1991071.yIU609i1g2@phil> (raw)
In-Reply-To: <3185764.oiGErgHkdL@diego>

Am Freitag, 7. Oktober 2022, 13:54:31 CEST schrieb Heiko Stübner:
> Am Donnerstag, 6. Oktober 2022, 09:08:14 CEST schrieb Jisheng Zhang:
> > make the riscv_cpufeature_patch_func() scan all ISA extensions rather
> > than limited feature macros.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>

[...]

> > @@ -127,7 +124,7 @@ asm volatile(ALTERNATIVE_2(						\
> >  	"add a0, a0, %0\n\t"						\
> >  	"2:\n\t"							\
> >  	"bltu a0, %2, 3b\n\t"						\
> > -	"nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,		\
> > +	"nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\
> 
> hmm, would it make sense to also at the same time extend the errata_id
> in the alternatives struct to unsigned long?
> 
> Right now it's a unsigned int, and we're already at bit30 with the current extensions.
> 
> Otherwise the idea is pretty neat of allowing easy handling for all extensions
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>

I think I might need to take that back ... with this change each
cpufeature is tightly coupled to real extension ids, but what about
cpufeatures that do not match directly to an extension?

I.e. ZICBOM + fast-unaligned-access [0] (coming from a dt-property)
or only viable with extension 1+2+3?


Heiko


[0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe&id=9be297f7ed349945cccc85f8df9d90e5ab68c1d9



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  reply	other threads:[~2022-10-13 13:47 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-06  7:08 [PATCH 0/8] riscv: improve boot time isa extensions handling Jisheng Zhang
2022-10-06  7:08 ` [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2022-10-06 13:10   ` Andrew Jones
2022-10-06 17:44     ` Andrew Jones
2022-10-07  9:18   ` Heiko Stübner
2022-10-08 13:06   ` Conor Dooley
2022-10-08 13:59     ` Jisheng Zhang
2022-10-13  5:37       ` Conor Dooley
2022-10-06  7:08 ` [PATCH 2/8] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2022-10-06 13:12   ` Andrew Jones
2022-10-07  9:38   ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2022-10-06 13:15   ` Andrew Jones
2022-10-07  9:22   ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2022-10-06 13:31   ` Andrew Jones
2022-10-07 11:54   ` Heiko Stübner
2022-10-13 13:28     ` Heiko Stuebner [this message]
2022-10-06  7:08 ` [PATCH 5/8] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2022-10-06 13:36   ` Andrew Jones
2022-10-06  7:08 ` [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2022-10-06 13:36   ` Andrew Jones
2022-10-07 15:11   ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 7/8] riscv: cpu_relax: switch " Jisheng Zhang
2022-10-06 13:28   ` kernel test robot
2022-10-06 13:37   ` Andrew Jones
2022-10-07 15:12   ` Heiko Stübner
2022-10-07 18:14   ` kernel test robot
2022-10-06  7:08 ` [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2022-10-06 13:38   ` Andrew Jones
2022-10-07 15:12   ` Heiko Stübner
2022-10-13 16:20 ` [PATCH 0/8] riscv: improve boot time isa extensions handling Andrew Jones
2022-10-29  9:56 ` Andrew Jones
2022-10-29 11:38   ` Jisheng Zhang
2022-10-30 16:03   ` Jisheng Zhang

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