Re: [PATCH] riscv: make t-head erratas depend on MMU

[<Conor.Dooley@microchip.com>]

On 07/09/2022 18:58, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Mittwoch, 7. September 2022, 18:35:50 CEST schrieb Conor.Dooley@microchip.com:
>> On 07/09/2022 16:49, Heiko Stuebner wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Both basic extensions of SVPBMT and ZICBOM depend on CONFIG_MMU.
>>> Make the T-Head errata implementations of the similar functionality
>>> also depend on it to prevent build errors.
>>>
>>> Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head")
>>> Fixes: d20ec7529236 ("riscv: implement cache-management errata for T-Head SoCs")
>>> Reported-by: kernel test robot <lkp@intel.com>
>>
>> In case anyone cares:
>> Link: https://lore.kernel.org/all/202209070536.lIefsBuR-lkp@intel.com/
>>
>>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>> ---
>>>  arch/riscv/Kconfig.erratas | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
>>> index 6850e9389930..f3623df23b5f 100644
>>> --- a/arch/riscv/Kconfig.erratas
>>> +++ b/arch/riscv/Kconfig.erratas
>>> @@ -46,7 +46,7 @@ config ERRATA_THEAD
>>>
>>>  config ERRATA_THEAD_PBMT
>>>         bool "Apply T-Head memory type errata"
>>> -       depends on ERRATA_THEAD && 64BIT
>>> +       depends on ERRATA_THEAD && 64BIT && MMU
>>>         select RISCV_ALTERNATIVE_EARLY
>>>         default y
>>>         help
>>> @@ -57,7 +57,7 @@ config ERRATA_THEAD_PBMT
>>>
>>>  config ERRATA_THEAD_CMO
>>>         bool "Apply T-Head cache management errata"
>>> -       depends on ERRATA_THEAD
>>> +       depends on ERRATA_THEAD && MMU
>>
>> "Random" thought/question:
>> These two (and the sifive) errata all use oneliner depends
>> but the PMU series of yours has:
>> config ERRATA_THEAD_PMU
>>       bool "Apply T-Head PMU errata"
>>       depends on ERRATA_THEAD
>>       depends on RISCV_PMU_SBI
>>
>> What's the rationale behind not oneliner-ing that one?
> 
> probably not thinking too much about it beforehand ;-) .
> 
> But yes going with one line is probably nicer, so I transplanted this
> comment over to the sbi-pmu patch, for when a v4 might be necessary.

Ehh my OCD just got triggered by it that's all.
I've been kinda wondering in general what's a good policy for depends
lines, seems like one of those things that just varies wildly tbh...

> 
> 
> Heiko
> 
> 
>> That's obviously orthogonal to this patch though, so:
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>
>>>         select RISCV_DMA_NONCOHERENT
>>>         default y
>>>         help
>>> --
>>> 2.35.1
>>>
>>>
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>>
>>
> 
> 
> 
> 

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