From: hch@infradead.org (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH] RISC-V: Add the directive for alignment of stvec's value
Date: Thu, 2 Aug 2018 03:05:18 -0700 [thread overview]
Message-ID: <20180802100518.GA4144@infradead.org> (raw)
In-Reply-To: <1529545207-26999-1-git-send-email-zong@andestech.com>
On Thu, Jun 21, 2018 at 09:40:07AM +0800, Zong Li wrote:
> The stvec's value must be 4 byte alignment by specification definition.
> This directive avoids to stvec be set the non-alignment value by the
> following code in head.S
>
> /* Point stvec to virtual address of intruction after satp write */
> la a0, 1f
> add a0, a0, a1
> csrw stvec, a0
>
> Signed-off-by: Zong Li <zong@andestech.com>
Just noticed this didn't get picked up yet, so:
Reviewed-by: Christoph Hellwig <hch@lst.de>
prev parent reply other threads:[~2018-08-02 10:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-21 1:40 [PATCH] RISC-V: Add the directive for alignment of stvec's value Zong Li
2018-08-02 0:38 ` Palmer Dabbelt
2018-08-02 1:26 ` Zong Li
2018-08-04 4:38 ` Palmer Dabbelt
2018-08-02 10:05 ` Christoph Hellwig [this message]
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