From: hch@infradead.org (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 3/8] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Date: Thu, 30 Aug 2018 07:40:10 -0700 [thread overview]
Message-ID: <20180830144010.GE11544@infradead.org> (raw)
In-Reply-To: <20180827184243.25344-4-palmer@sifive.com>
> +/* Returns the hart ID of the given device tree node, or -1 if the device tree
> + * node isn't a RISC-V hart. */
In addition to the comment formatting: we usually keep the description
near the implementation, not the header. It could also become a
kerneldoc comment for added clarity.
> +extern int riscv_of_processor_hartid(struct device_node *node);
No need to declare function prototypes in headers with the extern
attribute, btw.
next prev parent reply other threads:[~2018-08-30 14:40 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-27 18:42 [PATCH 0/8] RISC-V: Assorted Cleanups Palmer Dabbelt
2018-08-27 18:42 ` [PATCH 1/8] RISC-V: Provide a cleaner raw_smp_processor_id() Palmer Dabbelt
2018-08-30 14:37 ` Christoph Hellwig
2018-08-27 18:42 ` [PATCH 2/8] RISC-V: Don't set cacheinfo.{physical_line_partition, attributes} Palmer Dabbelt
2018-08-30 14:38 ` Christoph Hellwig
2018-08-30 19:50 ` [PATCH 2/8] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} Jeremy Linton
2018-08-27 18:42 ` [PATCH 3/8] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid Palmer Dabbelt
2018-08-28 18:50 ` Atish Patra
2018-08-30 14:40 ` Christoph Hellwig [this message]
2018-08-27 18:42 ` [PATCH 4/8] RISC-V: Filter ISA and MMU values in cpuinfo Palmer Dabbelt
2018-08-27 18:42 ` [PATCH 5/8] RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu Palmer Dabbelt
2018-08-30 14:41 ` Christoph Hellwig
2018-08-30 16:11 ` Atish Patra
2018-08-31 5:54 ` Christoph Hellwig
2018-08-31 21:18 ` Atish Patra
2018-09-06 9:45 ` Palmer Dabbelt
2018-09-06 9:45 ` Palmer Dabbelt
2018-08-27 18:42 ` [PATCH 6/8] RISC-V: Use mmgrab() Palmer Dabbelt
2018-08-30 14:41 ` Christoph Hellwig
2018-08-27 18:42 ` [PATCH 7/8] RISC-V: Comment on the TLB flush in smp_callin() Palmer Dabbelt
2018-08-30 14:42 ` Christoph Hellwig
2018-08-27 18:42 ` [PATCH 8/8] RISC-V: Disable preemption before enabling interrupts when booting secondary harts Palmer Dabbelt
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