From mboxrd@z Thu Jan 1 00:00:00 1970 From: jimw@sifive.com (Jim Wilson) Date: Fri, 12 Oct 2018 13:03:50 -0700 Subject: [PATCH] RISC-V: Add futex support. Message-ID: <20181012200350.5258-1-jimw@sifive.com> To: linux-riscv@lists.infradead.org List-Id: linux-riscv.lists.infradead.org Here is an attempt to add the missing futex support. I started with the MIPS version of futex.h and modified it until I got it working. I tested it on a HiFive Unleashed running Fedora Core 29 using the fc29 4.15 version of the kernel. This was tested against the glibc testsuite, where it fixes 14 nptl related testsuite failures. That unfortunately only tests the cmpxchg support, so I also used the testcase at the end of https://lwn.net/Articles/148830/ which tests the atomic_op functionality, except that it doesn't verify that the operations are atomic, which they obviously are. This testcase runs successfully with the patch and fails without it. I'm not a kernel expert, so there could be details I got wrong here. I wasn't sure about the memory model support, so I used aqrl which seemed safest, and didn't add fences which seemed unnecessary. I'm not sure about the copyright statements, I left in Ralf Baechle's line because I started with his code. Checkpatch reports some style problems, but it is the same style as the MIPS futex.h, and the uses of ENOSYS appear correct even though it complains about them. I don't know if any of that matters. Jim Signed-off-by: Jim Wilson --- arch/riscv/include/asm/futex.h | 129 +++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/riscv/include/asm/futex.h diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h new file mode 100644 index 000000000000..f36ccceda762 --- /dev/null +++ b/arch/riscv/include/asm/futex.h @@ -0,0 +1,129 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2006 Ralf Baechle (ralf at linux-mips.org) + * Copyright (c) 2018 Jim Wilson (jimw at sifive.com) + */ +#ifndef _ASM_FUTEX_H +#define _ASM_FUTEX_H + +#ifdef __KERNEL__ + +#include +#include +#include +#include + +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ +{ \ + uintptr_t __tmp; \ + if (__riscv_atomic) { \ + __enable_user_access(); \ + __asm__ __volatile__ ( \ + "1: " insn " \n" \ + "2: \n" \ + " .section .fixup,\"ax\" \n" \ + " .balign 4 \n" \ + "3: li %0,%5 \n" \ + " jump 2b,%3 \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " .balign " RISCV_SZPTR " \n" \ + " " RISCV_PTR " 1b, 3b \n" \ + " .previous \n" \ + : "+r" (ret), "=&r" (oldval), \ + "+m" (*uaddr), "=&r" (__tmp) \ + : "Jr" (oparg), "i" (-EFAULT) \ + : "memory"); \ + __disable_user_access(); \ + } else { \ + ret = -ENOSYS; \ + } \ +} + +static inline int +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +{ + int oldval = 0, ret = 0; + + pagefault_disable(); + + switch (op) { + case FUTEX_OP_SET: + __futex_atomic_op("amoswap.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op("amoadd.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_OR: + __futex_atomic_op("amoor.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ANDN: + __futex_atomic_op("amoand.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, ~oparg); + break; + case FUTEX_OP_XOR: + __futex_atomic_op("amoxor.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + default: + ret = -ENOSYS; + } + + pagefault_enable(); + + if (!ret) + *oval = oldval; + + return ret; +} + +static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + int ret = 0; + u32 val; + uintptr_t __tmp; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + if (__riscv_atomic) { + __enable_user_access(); + __asm__ __volatile__ ( + "1: lr.w.aqrl %1,%4 \n" + " bne %1,%z5,3f \n" + "2: sc.w.aqrl %3,%z6,%2 \n" + " bnez %3,1b \n" + "3: \n" + " .section .fixup,\"ax\" \n" + " .balign 4 \n" + "4: li %0,%7 \n" + " jump 3b,%3 \n" + " .previous \n" + " .section __ex_table,\"a\" \n" + " .balign " RISCV_SZPTR " \n" + " " RISCV_PTR " 1b, 4b \n" + " " RISCV_PTR " 2b, 4b \n" + " .previous \n" + : "+r" (ret), "=&r" (val), "=m" (*uaddr), "=&r" (__tmp) + : "m" (*uaddr), "Jr" (oldval), "Jr" (newval), + "i" (-EFAULT) + : "memory"); + __disable_user_access(); + } else { + ret = -ENOSYS; + } + + *uval = val; + return ret; +} + +#endif +#endif /* _ASM_FUTEX_H */ -- 2.19.0.rc0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F185EC6787C for ; Fri, 12 Oct 2018 20:04:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96BA620868 for ; Fri, 12 Oct 2018 20:04:11 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 12 Oct 2018 13:03:55 -0700 (PDT) Received: from rohan.guest.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i5-v6sm2882548pfo.107.2018.10.12.13.03.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Oct 2018 13:03:54 -0700 (PDT) From: Jim Wilson To: linux-riscv@lists.infradead.org Subject: [PATCH] RISC-V: Add futex support. Date: Fri, 12 Oct 2018 13:03:50 -0700 Message-Id: <20181012200350.5258-1-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181012_130406_852170_330E9B7E X-CRM114-Status: GOOD ( 20.45 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jim Wilson MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Message-ID: <20181012200350.2QoFJgxMbYF-lnTeGFvywNLRiqOYYEbVGAhJgrwCy_o@z> Here is an attempt to add the missing futex support. I started with the MIPS version of futex.h and modified it until I got it working. I tested it on a HiFive Unleashed running Fedora Core 29 using the fc29 4.15 version of the kernel. This was tested against the glibc testsuite, where it fixes 14 nptl related testsuite failures. That unfortunately only tests the cmpxchg support, so I also used the testcase at the end of https://lwn.net/Articles/148830/ which tests the atomic_op functionality, except that it doesn't verify that the operations are atomic, which they obviously are. This testcase runs successfully with the patch and fails without it. I'm not a kernel expert, so there could be details I got wrong here. I wasn't sure about the memory model support, so I used aqrl which seemed safest, and didn't add fences which seemed unnecessary. I'm not sure about the copyright statements, I left in Ralf Baechle's line because I started with his code. Checkpatch reports some style problems, but it is the same style as the MIPS futex.h, and the uses of ENOSYS appear correct even though it complains about them. I don't know if any of that matters. Jim Signed-off-by: Jim Wilson --- arch/riscv/include/asm/futex.h | 129 +++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/riscv/include/asm/futex.h diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h new file mode 100644 index 000000000000..f36ccceda762 --- /dev/null +++ b/arch/riscv/include/asm/futex.h @@ -0,0 +1,129 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (c) 2018 Jim Wilson (jimw@sifive.com) + */ +#ifndef _ASM_FUTEX_H +#define _ASM_FUTEX_H + +#ifdef __KERNEL__ + +#include +#include +#include +#include + +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ +{ \ + uintptr_t __tmp; \ + if (__riscv_atomic) { \ + __enable_user_access(); \ + __asm__ __volatile__ ( \ + "1: " insn " \n" \ + "2: \n" \ + " .section .fixup,\"ax\" \n" \ + " .balign 4 \n" \ + "3: li %0,%5 \n" \ + " jump 2b,%3 \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " .balign " RISCV_SZPTR " \n" \ + " " RISCV_PTR " 1b, 3b \n" \ + " .previous \n" \ + : "+r" (ret), "=&r" (oldval), \ + "+m" (*uaddr), "=&r" (__tmp) \ + : "Jr" (oparg), "i" (-EFAULT) \ + : "memory"); \ + __disable_user_access(); \ + } else { \ + ret = -ENOSYS; \ + } \ +} + +static inline int +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +{ + int oldval = 0, ret = 0; + + pagefault_disable(); + + switch (op) { + case FUTEX_OP_SET: + __futex_atomic_op("amoswap.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ADD: + __futex_atomic_op("amoadd.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_OR: + __futex_atomic_op("amoor.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + case FUTEX_OP_ANDN: + __futex_atomic_op("amoand.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, ~oparg); + break; + case FUTEX_OP_XOR: + __futex_atomic_op("amoxor.w.aqrl %1,%z4,%2", + ret, oldval, uaddr, oparg); + break; + default: + ret = -ENOSYS; + } + + pagefault_enable(); + + if (!ret) + *oval = oldval; + + return ret; +} + +static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + int ret = 0; + u32 val; + uintptr_t __tmp; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + if (__riscv_atomic) { + __enable_user_access(); + __asm__ __volatile__ ( + "1: lr.w.aqrl %1,%4 \n" + " bne %1,%z5,3f \n" + "2: sc.w.aqrl %3,%z6,%2 \n" + " bnez %3,1b \n" + "3: \n" + " .section .fixup,\"ax\" \n" + " .balign 4 \n" + "4: li %0,%7 \n" + " jump 3b,%3 \n" + " .previous \n" + " .section __ex_table,\"a\" \n" + " .balign " RISCV_SZPTR " \n" + " " RISCV_PTR " 1b, 4b \n" + " " RISCV_PTR " 2b, 4b \n" + " .previous \n" + : "+r" (ret), "=&r" (val), "=m" (*uaddr), "=&r" (__tmp) + : "m" (*uaddr), "Jr" (oldval), "Jr" (newval), + "i" (-EFAULT) + : "memory"); + __disable_user_access(); + } else { + ret = -ENOSYS; + } + + *uval = val; + return ret; +} + +#endif +#endif /* _ASM_FUTEX_H */ -- 2.19.0.rc0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv