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[85.230.190.116]) by smtp.gmail.com with ESMTPSA id q10-v6sm2295968ljj.3.2019.01.21.06.10.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 06:10:44 -0800 (PST) Received: from johan by xi.terra with local (Exim 4.91) (envelope-from ) id 1glaHg-0001iu-TD; Mon, 21 Jan 2019 15:10:40 +0100 Date: Mon, 21 Jan 2019 15:10:40 +0100 From: Johan Hovold To: Paul Walmsley Subject: Re: [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Message-ID: <20190121141040.GM3691@localhost> References: <20181215052154.24347-1-paul.walmsley@sifive.com> <20181215052154.24347-6-paul.walmsley@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181215052154.24347-6-paul.walmsley@sifive.com> User-Agent: Mutt/1.11.2 (2019-01-07) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190121_061047_960190_C9409732 X-CRM114-Status: GOOD ( 15.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , linux-kernel@vger.kernel.org, Rob Herring , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Dec 14, 2018 at 09:21:52PM -0800, Paul Walmsley wrote: > Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC > based around the SiFive U54-MC core complex and a TileLink > interconnect. > > This file is expected to grow considerably as more device drivers are > added to the kernel. > > Cc: Rob Herring > Cc: Mark Rutland > Cc: Palmer Dabbelt > Cc: Albert Ou > Cc: devicetree@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Paul Walmsley > Signed-off-by: Paul Walmsley > --- > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 +++++++++++++++++++++ > 1 file changed, 182 insertions(+) > create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi > > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > new file mode 100644 > index 000000000000..0ef314cf17b6 > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <1000000>; > + cpu0: cpu@0 { > + clock-frequency = <0>; > + compatible = "sifive,e51", "sifive,rocket0"; Looks like you forgot the currently required "riscv" compatible here and below. But perhaps it's the binding and arch code that should be revised instead (e.g. as per your discussion with Rob elsewhere in this thread). Johan _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv