From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <Anup.Patel@wdc.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <Atish.Patra@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v6 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
Date: Thu, 25 Apr 2019 01:42:30 -0700 [thread overview]
Message-ID: <20190425084230.GA3612@infradead.org> (raw)
In-Reply-To: <20190425083804.11991-3-anup.patel@wdc.com>
On Thu, Apr 25, 2019 at 08:38:37AM +0000, Anup Patel wrote:
> This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
> defines to asm/csr.h. We also use these defines in kernel/irq.c and
> express SIE/SIP flags in-terms of SCAUSE interrupt causes.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Looks good,
Reviewed-by: Christoph Hellwig <hch@lst.de>
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next prev parent reply other threads:[~2019-04-25 8:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-25 8:38 [PATCH v6 0/3] Allow accessing CSR using CSR number Anup Patel
2019-04-25 8:38 ` [PATCH v6 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel
2019-04-25 8:38 ` [PATCH v6 2/3] RISC-V: Add interrupt related SCAUSE defines " Anup Patel
2019-04-25 8:42 ` Christoph Hellwig [this message]
2019-04-25 8:38 ` [PATCH v6 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel
2019-05-01 0:11 ` [PATCH v6 0/3] Allow accessing CSR using CSR number Palmer Dabbelt
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