From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,T_DKIMWL_WL_HIGH,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A05FEC43219 for ; Thu, 2 May 2019 09:10:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6E98220873 for ; Thu, 2 May 2019 09:10:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZE/Nhv+y" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6E98220873 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LxPG8a6AgMtVjBJNVjhK4Wn30FOHzgX5xHz86LhkWc0=; b=ZE/Nhv+yopRTje NItekkUfj6RTAEvUO04W4FH2EDs0fDB79D9aT6M9hcgJv8gz5VcxqENJ0tmizSppmA80kHqFuhESr qsuVyImxrdWproMwI5jd2BnjELfBi4DRZiyJBXX48Sl6AZ0yiVonRqwqAcztkM0jNPyVoDdmXzMLU GbAowahDO/pwTfBBja00m/xs+dCGUtuVBX/gmi0iITaprZsFYKhfuJqpqUdK2AvV3RpChxsRyxuc0 xlTOxIdPdP2GSKwLCaj+5CfJtf14FL23LPIK10h7tizk0cgLUf1FwwhO6x63U+4RWUYzOqQPWQ07Z cwazm4wgRCXP0kSr7NFw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hM7jy-0001s4-Pr; Thu, 02 May 2019 09:10:54 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hM7jt-0001ja-GX for linux-riscv@lists.infradead.org; Thu, 02 May 2019 09:10:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D42CB374; Thu, 2 May 2019 02:10:48 -0700 (PDT) Received: from e107155-lin (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 00C993F5AF; Thu, 2 May 2019 02:10:46 -0700 (PDT) Date: Thu, 2 May 2019 10:10:44 +0100 From: Sudeep Holla To: Yash Shah Subject: Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller Message-ID: <20190502091044.GD12498@e107155-lin> References: <1556171696-7741-1-git-send-email-yash.shah@sifive.com> <1556171696-7741-2-git-send-email-yash.shah@sifive.com> <20190425101318.GA8469@e107155-lin> <20190426093358.GA28309@e107155-lin> <20190502004130.GA20802@bogus> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190502_021049_862655_46E150DB X-CRM114-Status: GOOD ( 25.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Rob Herring , aou@eecs.berkeley.edu, devicetree@vger.kernel.org, Palmer Dabbelt , linux-kernel@vger.kernel.org, Sachin Ghadi , Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 02, 2019 at 10:50:12AM +0530, Yash Shah wrote: > On Thu, May 2, 2019 at 6:11 AM Rob Herring wrote: > > > > On Tue, Apr 30, 2019 at 09:50:45AM +0530, Yash Shah wrote: > > > On Fri, Apr 26, 2019 at 3:04 PM Sudeep Holla wrote: > > > > > > > > On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > > > > > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla wrote: > > > > > > > > > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > > > > > Add device tree bindings for SiFive FU540 L2 cache controller driver > > > > > > > > > > > > > > Signed-off-by: Yash Shah > > > > > > > --- > > > > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 ++++++++++++++++++++++ > > > > > > > 1 file changed, 53 insertions(+) > > > > > > > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > new file mode 100644 > > > > > > > index 0000000..15132e2 > > > > > > > --- /dev/null > > > > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > @@ -0,0 +1,53 @@ > > > > > > > +SiFive L2 Cache Controller > > > > > > > +-------------------------- > > > > > > > +The SiFive Level 2 Cache Controller is used to provide access to fast copies > > > > > > > +of memory for masters in a Core Complex. The Level 2 Cache Controller also > > > > > > > +acts as directory-based coherency manager. > > > > > > > + > > > > > > > +Required Properties: > > > > > > > +-------------------- > > > > > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > > > > > + > > > > > > > +- cache-block-size: Specifies the block size in bytes of the cache > > > > > > > + > > > > > > > +- cache-level: Should be set to 2 for a level 2 cache > > > > > > > + > > > > > > > +- cache-sets: Specifies the number of associativity sets of the cache > > > > > > > + > > > > > > > +- cache-size: Specifies the size in bytes of the cache > > > > > > > + > > > > > > > +- cache-unified: Specifies the cache is a unified cache > > > > > > > + > > > > > > > +- interrupt-parent: Must be core interrupt controller > > > > > > > + > > > > > > > +- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) > > > > > > > + > > > > > > > +- reg: Physical base address and size of L2 cache controller registers map > > > > > > > + > > > > > > > +- reg-names: Should be "control" > > > > > > > + > > > > > > > > > > > > It would be good if you mark the properties that are present in DT > > > > > > specification and those that are added for sifive,fu540-c000-ccache > > > > > > > > > > I believe there isn't any property which is added explicitly for > > > > > sifive,fu540-c000-ccache. > > > > > > > > > > > > > reg and interrupts are generally optional for normal cache and may be > > > > required for cache controller like this. DT specification[1] covers > > > > only caches and not cache controllers. > > > > > > Are you suggesting something like this: > > > > > > Required Properties: > > > -------------------- > > > Standard Properties: > > > > I don't think we need this separation. > > Ok. Won't include this "Standard/Non-standard properties" separation > in the next revision of this patch. > Sorry if I created confusion. I just wanted a note saying all the properties in ePAPR/DeviceTree specification applies for this platform. That would help me check if the standard cacheinfo infrastruction works as is or not. -- Regards, Sudeep _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv