From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>
Cc: Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>,
linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
linux-riscv@lists.infradead.org
Subject: [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muiltiple PLIC instances
Date: Sat, 16 May 2020 12:09:00 +0530 [thread overview]
Message-ID: <20200516063901.18365-4-anup.patel@wdc.com> (raw)
In-Reply-To: <20200516063901.18365-1-anup.patel@wdc.com>
To distinguish interrupts from multiple PLIC instances, we use a
per-PLIC irq_chip instance with a different name.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/irqchip/irq-sifive-plic.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 2d3db927a551..e42fc082ad18 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,6 +60,7 @@
#define PLIC_ENABLE_THRESHOLD 0
struct plic_priv {
+ struct irq_chip chip;
struct cpumask lmask;
struct irq_domain *irqdomain;
void __iomem *regs;
@@ -76,6 +77,7 @@ struct plic_handler {
void __iomem *enable_base;
struct plic_priv *priv;
};
+static unsigned int plic_count;
static bool plic_cpuhp_setup_done;
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
@@ -164,20 +166,12 @@ static void plic_irq_eoi(struct irq_data *d)
writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
}
-static struct irq_chip plic_chip = {
- .name = "SiFive PLIC",
- .irq_mask = plic_irq_mask,
- .irq_unmask = plic_irq_unmask,
- .irq_eoi = plic_irq_eoi,
-#ifdef CONFIG_SMP
- .irq_set_affinity = plic_set_affinity,
-#endif
-};
-
static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
+ struct plic_priv *priv = d->host_data;
+
+ irq_domain_set_info(d, irq, hwirq, &priv->chip, d->host_data,
handle_fasteoi_irq, NULL, NULL);
irq_set_noprobe(irq);
return 0;
@@ -294,6 +288,14 @@ static int __init plic_init(struct device_node *node,
if (!priv)
return -ENOMEM;
+ priv->chip.name = kasprintf(GFP_KERNEL, "PLIC%d", plic_count++);
+ priv->chip.irq_mask = plic_irq_mask,
+ priv->chip.irq_unmask = plic_irq_unmask,
+ priv->chip.irq_eoi = plic_irq_eoi,
+#ifdef CONFIG_SMP
+ priv->chip.irq_set_affinity = plic_set_affinity,
+#endif
+
priv->regs = of_iomap(node, 0);
if (WARN_ON(!priv->regs)) {
error = -EIO;
@@ -383,9 +385,9 @@ static int __init plic_init(struct device_node *node,
}
pr_info("interrupt-controller at 0x%llx "
- "(interrupts=%d, contexts=%d, handlers=%d)\n",
+ "(interrupts=%d, contexts=%d, handlers=%d) (%s)\n",
(unsigned long long)iores.start, nr_irqs,
- nr_contexts, nr_handlers);
+ nr_contexts, nr_handlers, priv->chip.name);
set_handle_irq(plic_handle_irq);
return 0;
--
2.25.1
next prev parent reply other threads:[~2020-05-16 6:39 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-16 6:38 [PATCH 0/4] More improvements for multiple PLICs Anup Patel
2020-05-16 6:38 ` [PATCH 1/4] irqchip/sifive-plic: Setup cpuhp once after current handler is present Anup Patel
2020-05-16 12:11 ` Marc Zyngier
2020-05-16 12:52 ` Anup Patel
2020-05-16 13:30 ` Marc Zyngier
2020-05-16 16:28 ` Anup Patel
2020-05-17 8:02 ` Anup Patel
2020-05-16 6:38 ` [PATCH 2/4] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances Anup Patel
2020-05-16 12:20 ` Marc Zyngier
2020-05-16 12:53 ` Anup Patel
2020-05-16 6:39 ` Anup Patel [this message]
2020-05-16 12:29 ` [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muiltiple " Marc Zyngier
2020-05-16 13:01 ` Anup Patel
2020-05-16 13:16 ` Marc Zyngier
2020-05-16 16:38 ` Anup Patel
2020-05-18 8:14 ` Marc Zyngier
2020-05-18 9:00 ` Anup Patel
2020-05-16 6:39 ` [PATCH 4/4] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Anup Patel
2020-05-16 12:30 ` Marc Zyngier
2020-05-16 12:53 ` Anup Patel
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